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參數(shù)資料
| 型號： | CY28378OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 15/21頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK408/TITAN 845 48SSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 203MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
CY28378
........................ Document #: 38-07519 Rev. ** Page 3 of 21
23
24_48MHz/FS1
I/O
24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or
48-MHz non-spread spectrum output. This pin also serves as a
power-on strap option to determine device operating frequency as
described in Table 2. This output will be used as the reference clock
for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale
– G platforms, this output will be used as the reference clock for both
USB host controller and SIO devices. We recommend system designer
to configure this output as 48 MHz and “HIGH Drive” by setting Byte
[5], Bit [0] and Byte [9], Bit [7], respectively.150k internal pull up.
27
3V66_3/48MHz_1
O
48MHz or 66MHz Output: 3.3V output.
42
PWRDWN#
I
Power Down Control: 3.3V LVTTL compatible input that places the
device in power down mode when held low. 150k internal pull up.
26
SCLK
I
SMBus Clock Input: Clock pin for serial interface.
25
SDATA
I/O
SMBus Data Input: Data pin for serial interface.
20
RESET#
O (open-drain) System Reset Output: Open-drain system reset output.
35
IREF
I
Current Reference for CPU Output: A precision resistor is attached
to this pin which is connected to the internal current reference.
19
VTT_PWRGD#
I
Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL
input. VTT_PWRGD# is a level sensitive strobe used to determine
when FS0:4 and MULTSEL0:1 inputs are valid and OK to be sampled
(Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this
input will be ignored.
2, 9, 18, 24, 32, 39,
46
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
P
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66
output buffers, PCI output buffers, reference output buffers and
48-MHz output buffers. Connect to 3.3V.
5, 13, 21, 29, 36,
43, 47
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
G
Ground Connection: Connect all ground pins to the common system
ground plane.
34
VDD_CORE
P
3.3V Analog Power Connection: Power supply for core logic, PLL
circuitry. Connect to 3.3V.
33
GND_CORE
G
Analog Ground Connection: Ground for core logic, PLL circuitry.
Pin Description
Pin #
Name
Type
Description
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