參數(shù)資料
型號(hào): CY28349BOC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: FTG for Intel Pentium 4 CPU and Chipsets
中文描述: 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁(yè)數(shù): 17/22頁(yè)
文件大?。?/td> 174K
代理商: CY28349BOC
CY28349B
Document #: 38-07454 Rev. *A
Page 17 of 22
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Switching Characteristics
Over the Operating Range
[3]
Parameter
t
1
t
2
t
2
t
2
t
3
t
3
t
3
t
4
t
5
t
6
t
7
t
8
Output
Description
Test Conditions
Min.
45
175
0.5
1.0
175
0.5
1.0
Max.
55
700
2.0
4.0
700
2.0
4.0
150
500
500
3.5
200
Unit
%
ps
V/ns
V/ns
ps
V/ns
V/ns
ps
ps
ps
ns
ps
All
CPU
48MHz, REF
PCI, 3V66,
CPU
48MHz, REF
PCI, 3V66
CPU
3V66 [0:1]
PCI
3V66,PCI
CPU
Output Duty Cycle
[4]
Rise Time
Rising Edge Rate
Rising Edge Rate
Fall Time
Falling Edge Rate
Falling Edge Rate
CPU-CPU Skew
3V66-3V66 Skew
PCI-PCI Skew
3V66-PCI Clock Skew
Cycle-Cycle Clock Jitter
t
1A
/(t
1B
)
Measured at 20% to 80% of V
oh
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Measured at 80% to 20% of V
oh
Between 2.4V and 0.4V
Between 2.4V and 0.4V
Measured at Crossover
Measured at 1.5V
Measured at 1.5V
3V66 leads. Measured at 1.5V
Measured at Crossover t
8 =
t
8A
t
8B
With all outputs running
Measured at 1.5V t
9 =
t
9A
t
9B
Measured at 1.5V t
9 =
t
9A
t
9B
Measured at 1.5V t
9 =
t
9A
t
9B
Measured at 1.5V t
9 =
t
9A
t
9B
CPU and PCI clock stabilization from
power-up
Measured with test loads
[5, 6]
Measured with test loads
[6]
1.5
t
9
t
9
t
9
t
9
3V66
48MHz
PCI
REF
CPU, PCI
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Settle Time
250
350
500
1000
3
ps
ps
ps
ps
ms
CPU
CPU
Rise/Fall Matching
Overshoot
20%
V
oh
+
0.2
V
CPU
CPU
CPU
CPU
Undershoot
High-level Output Voltage
Low-level Output Voltage
Crossover Voltage
Measured with test loads
[6]
Measured with test loads
[6]
Measured with test loads
[6]
Measured with test loads
[6]
0.2
0.65
0.0
45%
of
0.65
V
V
V
V
V
oh
V
ol
V
crossover
0.74
0.05
55% of
0.74
Notes:
2.
3.
4.
5.
6.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
All parameters specified with loaded outputs.
Duty cycle is measured at 1.5V when V
= 3.3V. When V
= 2.5V, duty cycle is measured at 1.25V.
Determined as a fraction of 2*(Trp
Trn)/(Trp + Trn) Where Trp is a rising edge and Trn is an intersecting falling edge.
The test load is R
s
= 33.2W, R
p
= 49.9W in test circuit.
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