參數(shù)資料
型號(hào): CY28378OC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: FTG for Pentium 4 and Intel 845 Series Chipset
中文描述: 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁數(shù): 1/22頁
文件大小: 174K
代理商: CY28378OC
FTG for Pentium 4
and Intel
845 Series Chipset
CY28378
Cypress Semiconductor Corporation
Document #: 38-07519 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 28,2003
Features
C
ompatible with Intel
CK-Titan and CK-408 Clock
Synthesizer/Driver specifications
System frequency synthesizer for Intel Brookdale 845
and Brookdale – G Pentium 4
chipsets
Programmable clock output frequency with less than
1-MHz increment
Integrated fail-safe Watchdog timer for system
recovery
Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
Programmable 3V66 and PCI output frequency mode
Capable of generating system RESET after a Watchdog
timer time-out or a change in output frequency via
SMBus interface occurs
Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength support
Programmable output skew support
Power management control inputs
Available in 48-pin SSOP
Table 1. Frequency Table
CPU
3V66
PCI
REF
48M
24_48M
x 3
x 4
x 10
x 2
x 1
x 1
Note:
1.
Signals marked with ‘*’ and ‘**’ have internal pull-up and pull-down resistors, respectively.
~
Block Diagram
VDD_REF
REF0:1
CPUT[0:1], CPUC[0:1],
CPU_ITP, CPU_ITP#
XTAL
OSC
PLL Ref Freq
X2
X1
VDD_PCI
PCI_F0:2
SCLK
PLL 1
SMBus
Logic
VDD_48MHz
48MHz_0
SDATA
VDD_3V66
3V66_0:2
Divider
Network
VDD_CPU
*FS0:4
2
PWRDWN#
SSOP-48
VTT_PWRGD#
VDD_REF
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
*FS4/PCI0
PCI1
PCI2
GND_PCI
PCI3
PCI4
PCI5
PCI6
VDD_PCI
VTT_PWRGD#
RESET#
GND_48MHz
*FS0/48MHz_0
*FS1/24_48MHz
VDD_48MHz
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
REF0/MULTSEL0**
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWRDWN#*
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
GNDC_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3/48MHz_1
SCLK
SDATA
C
*MULTSEL0:1
PCI0:6
24_48MHz
RESET#
VDD_48MHz
3V66_3/48MHz_1
2
Fract.
Aligner
PLL2
Pin Configuration
[1]
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