參數(shù)資料
型號: CY28347ZCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
中文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6 X 14 MM, TSSOP-56
文件頁數(shù): 19/22頁
文件大小: 188K
代理商: CY28347ZCT
CY28347
Document #: 38-07352 Rev. *C
Page 19 of 22
AMD K7 processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
When the PD# signal is asserted LOW, all clocks are disabled
to a LOW level in an orderly fashion prior to removing power
from the CPU. When PD# is sampled LOW by two consecutive
rising edges of the CPUCS_C clock, then all affected clocks
are stopped in a LOW state after the next HIGH to LOW
transition or remains LOW. When in power-down (and before
power is removed), all outputs are synchronously stopped in a
LOW state (see
Figure 15
below), all PLLs are shut off, and
the crystal oscillator is disabled. When the device is shutdown,
the I2C function is also disabled.
Power Down Deassertion (K7 Mode)
When deasserted PD# to HIGH level, all clocks are enabled
and start running on the rising edge of the next full period in
order to guarantee a glitch-free operation, no partial clock
pulses.
PCI 33MHz
PWRDWN#
REF 14.318MHz
USB 48MHz
DDRT 133MHz
DDRC 133MHz
AGP 66MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
CPUOD_T 133MHz
CPUCS_T 133MHz
Figure 15. Power-down Assertion Timing Waveform (in K7 Mode)
PCI 33MHz
PWRDWN#
AGP 66MHz
REF 14.318MHz
USB 48MHz
<1.5 msec
DDRT 133MHz
DDRC 133MHz
CPUOD_T 133MHz
CPUCS_T 133MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
Figure 16. Power-down Deassertion Timing Waveform (in K7 Mode)
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