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參數(shù)資料
| 型號(hào)： | CY28341ZCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP2-56 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY28341ZCT |
CY28341
Document #: 38-07367 Rev. *A
Page 7 of 21
Byte 5: SDR/DDR Clock Register
Bit
7
@Pup
0
Pin#
45
Name
BUF_IN
threshold
voltage
FBOUT
DDRT/C5/SD
RAM(10,11)
DDRT/C4/SD
RAM(8,9)
DDRT/C3/SD
RAM(6,7)
DDRT/C2/SD
RAM(4,5)
DDRT/C1/SD
RAM(2,3)
DDRT/C0/SD
RAM(0,1)
Description
DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05VSDR Mode, BUF_IN
threshold setting. 0 = 1.35V, 1 = 1.25V
6
5
1
1
46
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
29,30
4
1
31,32
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
3
1
35,36
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
2
1
37,38
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1
1
41,42
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
0
1
43,44
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
Byte 6: Watchdog Register
Bit @Pup Pin#
7
1
6
0
Name
SRESET# 1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET# signal.
Frequency
Revert
out only.0 = selects frequency of existing H/W setting1 = selects frequency of the second to
last S/W setting (the software setting prior to the one that caused a system reboot).
WDTEST
WD-Test, ALWAYS program to
“
0.
”
WD Alarm This bit is set to
“
1
”
when the Watchdog times out. It is reset to
“
0
”
when the system clears the
WD time stamps (WD3:0).
WD3
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
.
WD2
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
.
WD1
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
.
WD0
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
.
Table 7. Watchdog Time Stamp
Description
26
This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time
5
4
0
0
3
2
1
0
0
0
0
0
WD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Off
1 second
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28341OCT | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28341OC | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28346 | Clock Synthesizer with Differential CPU Outputs |
| CY28346OC | CONN BNC PLUG CRIMP RG-TFE-59,62 |
| CY28346OCT | CONN BNC PLUG CRIMP RG-59,62 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28342 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-performance SiS645/650 Pentium 4 Clock Synthesizer |
| CY28342OC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28342OCT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY28342ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-performance SiS645/650 Pentium 4 Clock Synthesizer |
| CY28342ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-performance SiS645/650 Pentium 4 Clock Synthesizer |
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