參數(shù)資料
型號: CY28341ZCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
中文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6 X 14 MM, TSSOP2-56
文件頁數(shù): 18/21頁
文件大?。?/td> 189K
代理商: CY28341ZCT
CY28341
Document #: 38-07367 Rev. *A
Page 18 of 21
For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1)
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Note:
32. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same
length transmission line to the other signal of the pair (e.g., AGP) should be added.
Table 10. Signal Loading Table
Clock Name
Max Load (in pF)
20
30
30
REF (0:1), 48MHz (USB), 24_48MHz
AGP(0:2), SDRAM (0:11)
PCI_F(0:5)
DDRT/C (0:5), FBOUT
CPUT/C
CPUOD_T/C
CPUCS_T/C
See Figure 10
See Figure 8
See Figure 9
CLK Measurement Point
R
ref
R
tA1
CPUT
MULTSEL
CLK Measurement Point
R
LA1
R
D
R
LB1
R
LA2
R
LB2
R
tA2
R
tB1
R
tB2
C
LA
C
LB
T
PCB
T
PCB
CPUT#
Figure 10.
Table 11. Lumped Test Load Configuration
Component 0.7V Amplitude Value 1.0V Amplitude Value
R
tA1
, R
tA2
33
R
LA1
, R
LA2
49.9
T
PCB
3
50
Z
R
LB1
, R
LB2
R
D
R
tB1
, R
tB2
0
C
LA
, C
LB
2 pF
R
ref
475
w/mult0 = 1
0
3
50
Z
63
470
33
2 pF
221
w/mult0 = 0
Group Timing Relationships and Tolerances
[32]
Offset (ps) Tolerance (ps) Conditions
750
500
t
CSAGP
CPUCS to
AGP
t
AP
AGP to
PCI
CPUCS
Leads
AGP Leads
1,250
500
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