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參數(shù)資料
| 型號： | CY28329ZXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs |
| 中文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 290K |
| 代理商： | CY28329ZXCT |
CY28329
Document #: 38-07040 Rev. *E
Page 8 of 17
Switching Characteristics
Over the Operating Range
[8]
Parameter
Output
Description
Test Conditions
Min.
Max.
Unit
t
1
t
2
All
Output Duty Cycle
[9]
Measured at 1.5V
45
55
%
CPU
Rise Time
Measured differential waveform from
–0.35V to +0.35V
175
700
ns
t
2
USB, REF,
DOT
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
ns
t
2
t
3
PCI, 3V66
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
CPU
Fall Time
Measured differential waveform from
–0.35V to +0.35V
175
700
ps
t
3
USB, REF,
DOT
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
ns
t
3
t
4
t
5
t
5
t
6
t
7
t
8
PCI, 3V66
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
CPU
CPU-CPU Skew
Measured at Crossover
150
ps
3V66 [0:1]
3V66-3V66 Skew
Measured at 1.5V
500
ps
66BUFF[0:2]
66BUFF-66BUFF Skew
Measured at 1.5V
175
ps
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
3V66, PCI
3V66-PCI Clock Skew
3V66 leads. Measured at 1.5V
1.5
3.5
ns
CPU
Cycle-Cycle Clock Jitter
Measured at Crossover t
8 =
t
8A
– t
8B
With all outputs running
150
ps
t
9
t
9
t
9
t
9
t
10
3V66
Cycle-Cycle Clock Jitter
Measured at 1.5V t
9 =
t
9A
– t
9B
Measured at 1.5V t
9 =
t
9A
– t
9B
Measured at 1.5V t
9 =
t
9A
– t
9B
Measured at 1.5V t
9 =
t
9A
– t
9B
Measured at 1.5V
[10, 11]
Measured with test loads
[12, 13]
Measured with test loads
[13]
250
ps
USB, DOT
Cycle-Cycle Clock Jitter
350
ps
PCI
Cycle-Cycle Clock Jitter
500
ps
REF
Cycle-Cycle Clock Jitter
1000
ps
ALL
POR timing
1.0
4.0
ms
CPU
Rise/Fall Matching
235
mV
V
oh
CPU
High-level Output Voltage
including overshoot
0.92
1.45
V
V
ol
CPU
Low-level Output Voltage
including undershoot
Measured with test loads
[13]
–0.2
0.35
V
V
crossover
CPU
Crossover Voltage
Measured with test loads
[13]
0.250
0.550
V
Notes:
8. All parameters specified with loaded outputs.
9. Duty cycle is measured at 1.5V when V
DD
= 3.3V. When V
DD
= 2.5V, duty cycle is measured at 1.25V.
10.POR starts when V
reaches 1.5V.
11. All PULL-UPs must ramp at the same rate as V
.
12.Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trn is an intersecting falling edge.
13.The test load is R
s
= 33.2
, R
p
= 49.9
in test circuit.
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