參數(shù)資料
型號(hào): CY28329ZXCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): XO, clock
英文描述: 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs
中文描述: 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
文件頁(yè)數(shù): 6/17頁(yè)
文件大?。?/td> 290K
代理商: CY28329ZXCT
CY28329
Document #: 38-07040 Rev. *E
Page 6 of 17
Data Byte 4:
Bit
Pin#
33
Name
Pin Description
Type
R
R
R/W
Power On
Default
0
0
1
Bit 7
Bit 6
Bit 5
Reserved, set = 0
Reserved, set = 0
3V66_0 Output Enable
1 = Enabled; 0 = Disabled
3V66_1/VCH Output Enable
1 = Enabled; 0 = Disabled
3V66_5 Output Enable
1 = Enable; 0 = Disable
Note
:
This bit should be used when pin 24 is configured as
3V66_5 output. do not clear this bit when pin 24 is
configured as 66IN input.
66-MHz Buffered 2 Output Enable
1 = Enabled; 0 = Disabled
66-MHz Buffered 1 Output Enable
1 = Enabled; 0 = Disabled
66-MHz Buffered 0 Output Enable
1 = Enabled; 0 = Disabled
3V66_0
Bit 4
35
3V66_1/VCH
R/W
1
Bit 3
24
66IN/3V66_5
R/W
1
Bit 2
23
66BUFF2
R/W
1
Bit 1
22
66BUFF1
R/W
1
Bit 0
21
66BUFF0
R/W
1
Data Byte 5:
Bit
Pin#
Name
Pin Description
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Power On
Default
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved, set = 0
Reserved, set = 0
Tpd 66IN to 66BUFF propagation delay control
21,22,23
66BUFF [2:0]
38
DOT
DOT edge rate control
39
USB
USB edge rate control
Byte 6: Vendor ID
Bit
Description
Type
R
R
R
R
R
R
R
R
Power On
Default
0
0
0
0
1
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
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