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參數(shù)資料
| 型號(hào)： | CY28326OXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Single Pole Normally Open: 1-Form-A |
| 中文描述： | 333.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | LEAD FREE, SSOP-48 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 288K |
| 代理商： | CY28326OXC |
CY28326
Document #: 38-07616 Rev. *A
Page 13 of 23
PCI_STP# Assertion
[2]
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function.
The set-up time for capturing PCI_STP# going LOW is 10 ns
(t
SU
). (See
Figure 7
.)
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI
clocks to
resume running in a synchronous manner within two PCI clock
periods after PCI_STP# transitions to a high level.
Note:
2.
The PCI STOP function is controlled by PCI_STP# pin number 19.
CPU_STP#
CPUT
CPUC
CPU Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 6. CPU_STP# De-assertion Waveform
Tsu
PCI_STP#
PCI_F
PCI
Figure 7. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F
PCI
Tsu
Figure 8. PCI_STP# Deassertion Waveform
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