參數(shù)資料
型號: CY28326OXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Single Pole Normally Open: 1-Form-A
中文描述: 333.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: LEAD FREE, SSOP-48
文件頁數(shù): 11/23頁
文件大?。?/td> 288K
代理商: CY28326OXC
CY28326
Document #: 38-07616 Rev. *A
Page 11 of 23
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
CL ..................................................Crystal load capacitance
CLe ................................................Actual loading seen by
crystal using standard value trim capacitors
Ce ..................................................External trim capacitors
Cs...........................................CStray capacitance (trace,etc)
Ci ............. Internal capacitance (lead frame, bond wires etc)
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function. When PD# is low, all clocks are driven
to a LOW value and held there and the VCO and PLLs are also
powered down. All clocks are shut down in a synchronous
manner so as not to cause glitches while transitioning to the
low ‘stopped’ state.
PD# – Assertion
When PD# is sampled low by two consecutive rising edges of
CPUC clock then all clock outputs (except CPU) clocks must
be held low on their next high to low transition. CPU clocks
must be driven high with a value of 2x Iref and CPUC undriven.
Due to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce
= 2 * CL - (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
PD#
AGP, 66MHz
48MHz
PCI, 33MHz
REF, 14.31818
SRC, 25MHz
CPUC,
133MHz
CPUT, 133MHz
Figure 3. Power-down Assertion Timing Waveforms
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