參數(shù)資料
型號： CY28317PVXC-2
廠商： Silicon Laboratories Inc
文件頁數(shù)： 9/20頁
文件大?。?/td> 0K
描述： IC CLK FTG VIA PL/E133T 48SSOP
標準包裝： 30
類型： 時鐘/頻率發(fā)生器
PLL： 是
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:20
差分 - 輸入:輸出： 無/是
頻率 - 最大： 248MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
CY28317-2
..................... Document #: 38-07094 Rev. *B Page 17 of 20
PCI Clock Outputs, PCI (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on the rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on the rising and falling edges at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on the rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250
ps
tSK
Output Skew
Measured on the rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on the rising
edge at 1.5V. CPU leads PCI output.
1.5
4
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
30
REF Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on the rising and falling edges at 1.5V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on the rising and falling edges at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28317PVXC-2T 功能描述:時鐘發(fā)生器及支持產(chǎn)品 NB Clk VIA SDRAM Chipsets / Tualatin RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
CY28317ZC-2 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets
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CY28322 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers
CY28322-2 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
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