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參數(shù)資料
| 型號： | CY28317PVXC-2 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK FTG VIA PL/E133T 48SSOP |
| 標準包裝： | 30 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 248MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 48-SSOP |
| 包裝： | 管件 |
CY28317-2
....................... Document #: 38-07094 Rev. *B Page 9 of 20
Bit 3
RST_EN_FC
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2
WD_TO_STATUS
0
Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write)
Bit 1
WD_EN
0
0 = Stop and reload Watchdog Timer. Unlock CY28317-2 from recovery
frequency mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change
occurs.
Note: CY28317-2 will generate a system reset, reload a recovery frequency,
and lock itself into a recovery frequency mode after a Watchdog Timer time-out
occurs. Under recovery frequency mode, CY28317-2 will not respond to any
attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28317-2 from its recovery frequency mode by clearing
the WD_EN bit.
Bit 0
CPU0:1_DRV
0
CPU0:1 clock output drive strength
0 = Normal
1 = High Drive
Byte 9: System RESET and Watchdog Timer Register (continued)
Bit
Name
Default
Pin Description
Byte 10: Skew Control Register
Bit
Name
Default
Description
Bit 7
CPU0:1_Skew2
0
CPU 0:1 output skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 6
CPU0:1_Skew1
0
Bit 5
CPU0:1_Skew0
0
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
CPUT&C_Skew1
0
CPUT and CPUC output skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 0
CPUT&C_Skew0
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28317PVXC-2T | 功能描述:時鐘發(fā)生器及支持產品 NB Clk VIA SDRAM Chipsets / Tualatin RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28317ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets |
| CY28317ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets |
| CY28322 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY28322-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs |
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