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參數(shù)資料
| 型號(hào)： | CY28317PVXC-2 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK FTG VIA PL/E133T 48SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 248MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
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CY28317-2
..................... Document #: 38-07094 Rev. *B Page 14 of 20
How to Program CPU Output Frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * (N+3)/(M+3)
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value register and M-Value register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 4.
The ratio of (N+3) and (M+3) need to be greater than “1”
[(N+3)/(M+3) > 1].
The following table lists set of N and M values for different
frequency output ranges.This example uses a fixed value for
the M-Value register and selects the CPU output frequency by
changing the value of the N-Value register.
WD_TIMER[4:0]
These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the
prescaler.
The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit.
WD_PRE_SCALER
0 = 150 ms
1 = 2.5 sec
RST_EN_WD
This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
RST_EN_FC
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
Table 7. Register Summary (continued)
Name
Description
Table 8. Examples of N and M Value for Different CPU Frequency Range
Frequency Ranges
Gear Constants
Fixed Value for
M-Value Register
Range of N-Value Register
for Different CPU Frequency
50 MHz – 129 MHz
48.00741
93
97–255
130 MHz – 248 MHz
48.00741
45
127–245
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28317PVXC-2T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 NB Clk VIA SDRAM Chipsets / Tualatin RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28317ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets |
| CY28317ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets |
| CY28322 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY28322-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs |
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