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參數(shù)資料
| 型號(hào)： | CY26211 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 87K |
| 代理商： | CY26211 |
PRELIMINARY
T1/E1 Clock Generator
CY26200
Cypress Semiconductor Corporation
Document #: 38-07335 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
Features
Benefits
Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
3.3V operation
High-performance PLL tailored for T1/E1 clock generation
Meets critical timing requirements in complex system designs
Enables application compatibility
Part Number
CY26200
Outputs
1
Input Frequency Range
19.44 MHz
Output Frequencies
1.544 MHz/2.048 MHz (selectable)
Logic Block Diagram
19.44 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
Q
P
VCO
VDD
VSS
Φ
CLK1
8-pin SOIC
CY26200
Pin Configuration
1
2
3
4
XOUT
XIN
FS
VDD
AVSS
VSS
CLK1
5
6
7
8
AVDD
AVDD
AVSS
Table 1: CY26200 Frequency Select Option
Frequency Select
0
1
CLK1
1.544
2.048
Unit
MHz
MHz
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