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參數(shù)資料
| 型號： | CY25200ZXC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Paired Cable; Number of Conductors:24; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:12; Conductor Material:Copper; Features:Traditional Analog Audio Applications RoHS Compliant: Yes |
| 中文描述： | 可編程擴(kuò)頻時(shí)鐘發(fā)生器減少電磁干擾 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 280K |
| 代理商： | CY25200ZXC |
CY25200
Document #: 38-07633 Rev. *A
Page 7 of 11
Absolute Maximum Rating
Supply Voltage (VDD).......................................–0.5 to +7.0V
DC Input Voltage......................................–0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing).....–55
°
C to +125
°
C
Junction Temperature................................ –40
°
C to +125
°
C
Data Retention @ Tj = 125
°
C............................... > 10 Years
Package Power Dissipation......................................350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Notes:
3. Rated for 10 years.
4. Not 100% tested, guaranteed by design.
5. I
VDD
currents specified for SSCLK1/2/3/4/5/6 = 33.33 MHz with CLKIN = 14.318 MHz and 15 pF on all the output clocks.
Recommended Crystal Specifications
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
Description
Comments
Min. Typ. Max. Unit
8
6
Nominal Crystal Frequency
Nominal Load Capacitance
Equivalent Series Resistance (ESR)
Ratio of Third Overtone Mode ESR to
Fundamental Mode ESR
Crystal Drive Level
Recommended Operating Conditions
Parallel resonance, fundamental mode, AT cut
Internal load caps
Fundamental mode
Ratio used because typical R
1
values are much
less than the maximum spec
No external series resistor assumed
30
30
25
MHz
pF
3
DL
0.5
2
mW
Parameter
Description
Min.
3.135
3.135
2.375
0
–
–
3
Typ.
3.3
3.3
2.5
–
–
–
–
Max.
3.465
3.465
2.625
70
15
15
200
Unit
V
V
V
°C
pF
pF
MHz
V
DD
V
DDLHI
V
DDLLO
T
AC
C
LOAD
C
LOAD
F
SSCLK-HighVoltage
Operating Voltage
Operating Voltage
Operating Voltage
Ambient Commercial Temp
Max. Load Capacitance V
DD
/V
DDL
= 3.3V
Max. Load Capacitance V
DDL
= 2.5V
SSCLK1/2/3/4/5/6 when V
DD
= A
VDD
= V
DDL
=
3.3 V
SSCLK5/6 when V
DD
= 3.3.V and V
DDL
= 2.5V
REFOUT when V
DD
= A
VDD
= 3.3.V and V
DDL
=
3.3V or 2.5V
Clock Input
Crystal Input
Power-up time for all V
DD
s to reach minimum
specified voltage (power ramps must be
monotonic)
F
SSCLK-LowVoltage
R
EFOUT
3
8
–
–
166
166
MHz
MHz
f
REF1
f
REF2
t
PU
8
8
–
–
–
166
30
500
MHz
MHz
ms
0.05
DC Electrical Specifications
Parameter
[4]
I
OH3.3
Output High Current
I
OL3.3
Output Low Current
I
OH2.5
Output High Current
I
OL2.5
Output Low Current
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
VDD[5]
Supply Current
I
VDDL2.5[5]
Supply Current
I
VDDL3.3[5]
Supply Current
I
DDS
Power-Down Current
I
OHZ
I
OLZ
Name
Description
Min.
10
10
8
8
0.7
0
–
–
–
–
–
Typ.
12
12
16
16
–
–
–
–
–
–
–
Max.
–
–
–
–
1.0
0.3
33
20
26
50
10
Unit
mA
mA
mA
mA
V
DD
V
DD
mA
mA
mA
uA
uA
V
OH
= V
DD
– 0.5V, V
DD
/V
DDL
= 3.3V
V
OL
= 0.5V, V
DD
/V
DDL
= 3.3V
V
OH
= V
DDL
– 0.5V, V
DDL
= 2.5V
V
OL
= 0.5V, V
DDL
= 2.5V
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
AV
DD
/V
DD
Current
V
DDL
Current (V
DDL
= 2.625V)
V
DDL
Current (V
DDL
= 3.465V)
V
DD
= V
DDL
= AV
DD
= 3.465V
V
DD
= V
DDL
= AV
DD
= 3.465V
Output Leakage
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY25200ZXC_XXXW | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Spread Spectrum Clock Generator for EMI Reduction |
| CY25200ZXC_XXXWT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Spread Spectrum Clock Generator for EMI Reduction |
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| CY25200-ZXC002AT | 功能描述:鎖相環(huán) - PLL Spectrum Clk Genratr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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