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參數(shù)資料
| 型號(hào)： | CY25200ZXC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Paired Cable; Number of Conductors:24; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:12; Conductor Material:Copper; Features:Traditional Analog Audio Applications RoHS Compliant: Yes |
| 中文描述： | 可編程擴(kuò)頻時(shí)鐘發(fā)生器減少電磁干擾 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 280K |
| 代理商： | CY25200ZXC |
Programmable Spread Spectrum
Clock Generator for EMI Reduction
CY25200
Cypress Semiconductor Corporation
Document #: 38-07633 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 22, 2004
Features
Wide operating output (SSCLK) frequency range
— 3–200 MHz
Programmable spread spectrum with nominal 31.5-kHz
modulation frequency.
Center spread: ±0.25% to ±2.5%
Down spread: –0.5% to –5.0%
Input frequency range:
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
Integrated phase-locked loop (PLL)
Programmable crystal load capacitor tuning array
Low cycle-to-cycle Jitter
3.3V operation with 2.5V output clock drive option
Spread spectrum On/Off function
Power-down or Output Enable function
Output frequency select option
Benefits
Suitable for most PC peripherals, networking, and consum-
er applications.
Provides wide range of spread percentages for maximum
EMI reduction, to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development
and manufacturing costs and time-to-market.
Eliminates the need for expensive and difficult to use higher
order crystals.
Internal PLL generates up to 200 MHz outputs, and can
generate custom frequencies from an external crystal or a
driven source.
Enables fine-tuning of output clock frequency by adjusting
C
Load
of the crystal. Eliminates the need for external C
Load
capacitors.
Application compatibility in standard and low-power sys-
tems.
Provides ability to enable or disable spread spectrum with
an external pin.
Enables low-power state or output clocks to High-Z state.
Divider
Bank 1
PLL
SSCLK3
Q
P
VCO
Φ
SSCLK2
SSCLK4
SSCLK5/REFOUT/CP2
SSCLK6/REFOUT/CP3
Divider
Bank 2
Output
Select
Matrix
SSCLK1
Logic Block Diagram
VDDL
AVSS
AVDD
VSS
VSSL
VDD
CP0
CP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
CP1
SSCLK3
SSCLK1
XIN
VDD
AVDD
XOUT
CP0
AVSS
SSCLK2
SSCLK6
/REFOUT/CP3
SSCLK5
/REFOUT/CP2
VDDL
SSCLK4
Pin Configuration
2
3
5
13
11
6
4
10
7
8
9
12
14
15
XIN/CLKIN
OSC.
XOUT
C
XIN
1
C
XOUT
16
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| CY25702XZZZ | Programmable High-Frequency Crystal Oscillator (XO) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY25200ZXC_XXXW | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Spread Spectrum Clock Generator for EMI Reduction |
| CY25200ZXC_XXXWT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Spread Spectrum Clock Generator for EMI Reduction |
| CY25200-ZXC001A | 制造商:Cypress Semiconductor 功能描述: |
| CY25200-ZXC002A | 制造商:Rochester Electronics LLC 功能描述:PROGRAMMABLE SPREAD SPECTRUM CLOCK GENERATOR. TSSOP16 - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY25200-ZXC002AT | 功能描述:鎖相環(huán) - PLL Spectrum Clk Genratr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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