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參數(shù)資料
| 型號： | CY241V8A-01 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MPEG Clock Generator with VCXO(帶VCXO的MPEG時鐘發(fā)生器) |
| 中文描述： | 的MPEG時鐘發(fā)生器，石英振蕩器（帶石英振蕩器的時鐘發(fā)生器的MPEG） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 67K |
| 代理商： | CY241V8A-01 |
CY241V08A-01,04
CY241V8A-01
Document #: 38-07656 Rev. *C
Page 4 of 6
AC Electrical Specifications
(V
DD
= 3.3V)
[3]
Parameter
[3]
DC
Output Duty Cycle
ER
OR
Rising Edge Rate –01
Voltage and Timing Definitions
Note:
3. Not 100% tested.
Name
Description
Min.
45
0.8
Typ.
50
1.4
Max.
55
–
Unit
%
V/ns
Duty Cycle is defined in
Figure 1
, 50% of V
DD
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF See
Figure 2
.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See
Figure 2
.
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF See
Figure 2
.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See
Figure 2
.
Peak-to-peak period jitter
ER
OF
Falling Edge Rate –01
0.8
1.4
–
V/ns
ER
OR
Rising Edge Rate –04
0.7
1.1
–
V/ns
ER
OF
Falling Edge Rate –04
0.7
1.1
–
V/ns
t
9
t
10
Clock Jitter
PLL Lock Time
–
–
–
–
100
3
ps
ms
Test and Measurement Set-up
0.1
μ
F
VDD
Outputs
C
LOAD
GND
DUT
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Figure 1. Duty Cycle Definition
Clock
Output
t
3
t
4
V
DD
80% of V
DD
20% of V
DD
0V
Figure 2. ER = (0.6 x V
DD
)/t
3
, EF = (0.6 x V
DD
)/t
4
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| CY241V8ASXC-01 | 功能描述:鎖相環(huán) - PLL MPEG Clk Genratr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY241V8ASXC-01T | 功能描述:鎖相環(huán) - PLL MPEG Clk Genratr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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