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參數(shù)資料
| 型號(hào)： | CY24207 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MediaClock PDP Clock Generator |
| 中文描述： | MediaClock等離子時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 46K |
| 代理商： | CY24207 |
MediaClock
PDP Clock Generator
CY24207
Cypress Semiconductor Corporation
Document #: 38-07553 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised July 31, 2003
Features
Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
VCXO with Analog Adjust
3.3V operation
Benefits
Internal PLL with up to 400-MHz internal operation
Meets critical timing requirements in complex system
designs
Large ±200-ppm range, better linearity
Enables application compatibility
Part Number
CY24207-1
Outputs
4
Input Frequency
27-MHz Crystal Input
Output Frequency Range
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/67.357642 MHz (frequency selectable)
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/68.400599 MHz (frequency selectable)
CY24207-2
4
27-MHz Crystal Input
Frequency Select Options
OE
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
CLK1/CLK2 (-1)
[1]
off
off
off
off
54
53.946053 (–1 ppm)
67.425
67.357642 (3.8 ppm)
CLK1/CLK2 (-2)
[1]
off
off
off
off
54
53.946053 (–1 ppm)
67.425
68.400599(–8.8 ppm)
REFCLK 1/2
27
27
27
27
27
27
27
27
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Note:
1.
“off” = output is driven high.
Block Diagram
XIN
XOUT
OUTPUT
MULAND
DIVIDERS
PLL
OSC.
CLK1
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
FS0
FS1
CLK2
REFCLK1
VSSL
VDD
16-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
FS0
CLK2
XIN
VDD
AVDD
XOUT
VCXO
AVSS
REFCLK1
OE
FS1
VDDL
Pin Configuration
OE
VCXO
CLK1
2
REFCLK2
REFCLK2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY24207ZC-1 | MediaClock PDP Clock Generator |
| CY24207ZC-1T | MediaClock PDP Clock Generator |
| CY24207ZC-2 | MediaClock PDP Clock Generator |
| CY24207ZC-2T | MediaClock PDP Clock Generator |
| CY25200 | Programmable Spread Spectrum Clock Generator for EMI Reduction |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY24207ZC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24207ZC-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24207ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24207ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
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