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參數(shù)資料
| 型號： | CY24207 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MediaClock PDP Clock Generator |
| 中文描述： | MediaClock等離子時鐘發(fā)生器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 46K |
| 代理商： | CY24207 |
CY24207
Document #: 38-07553 Rev. *A
Page 4 of 6
Test and Measurement Set-up
Voltage and Timing Definitions
Note:
2.
Not 100% tested.
AC Electrical Specifications
Parameter
[2]
DC
Output Duty Cycle
ER
Rising Edge Rate
Name
Description
Min.
45
0.8
Typ.
50
1.4
Max.
55
Unit
%
V/ns
Duty Cycle is defined in
Figure 1
; t1/t2, 50% of V
DD
Output Clock Edge Rate, Measured from 20% to
80% of V
DD
, C
LOAD
= 15 pF. See
Figure 2
.
Output Clock Edge Rate, Measured from 80% to
20% of V
DD
, C
LOAD
= 15 pF. See
Figure 2
.
CLK1, CLK2 Peak-Peak period jitter
EF
Falling Edge Rate
0.8
1.4
V/ns
t
9
t
10
Clock Jitter
PLL Lock Time
120
ps
ms
3
0.1
μ
F
V
DDs
Outputs
C
LOAD
GND
DUT
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Figure 1. Duty Cycle Definition
Clock
Output
t
3
t
4
V
DD
80% of V
DD
20% of V
DD
0V
Figure 2. ER = (0.6 x V
DD
) /t3, EF = (0.6 x V
DD
) /t4
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| CY24207ZC-1 | MediaClock PDP Clock Generator |
| CY24207ZC-1T | MediaClock PDP Clock Generator |
| CY24207ZC-2 | MediaClock PDP Clock Generator |
| CY24207ZC-2T | MediaClock PDP Clock Generator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY24207ZC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24207ZC-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24207ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24207ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock PDP Clock Generator |
| CY24210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
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