參數(shù)資料
型號(hào): CY2313ANZSC-1
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
中文描述: 2313 SERIES, LOW SKEW CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 0.300 INCH, MO-119, SOIC-28
文件頁(yè)數(shù): 4/8頁(yè)
文件大?。?/td> 90K
代理商: CY2313ANZSC-1
CY2313ANZ
Document #: 38-07144 Rev. *A
Page 4 of 8
Switching Waveforms
Switching Characteristics
[4]
Over the Operating Range
Parameter
Name
Test Conditions
Min.
Typ.
Max.
100
55.0
4.0
4.0
+250
5.0
5.0
12
30
Unit
MHz
%
V/ns
V/ns
ps
ns
ns
ns
ns
Maximum Operating Frequency
Duty Cycle
[3,5]
= t
2
÷
t
1
Rising Edge Rate
[3]
Falling Edge Rate
[3]
Output to Output Skew
[3]
SDRAM Buffer LH Prop. Delay
[3]
SDRAM Buffer HL Prop. Delay
[3]
SDRAM Buffer Enable Delay
[3]
SDRAM Buffer Disable Delay
[3]
Measured at 1.5V
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
45.0
0.9
0.9
250
1.0
1.0
1.0
1.0
50.0
1.5
1.5
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Notes:
4.
5.
3.5
3.5
5
20
All parameters specified with loaded outputs.
Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns.
Duty Cycle Timing
t
1
t
2
1.5V
1.5V
1.5V
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t
4
Output-Output Skew
1.5V
t
5
OUTPUT
OUTPUT
1.5V
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