參數(shù)資料
型號(hào): CY2285
廠商: Cypress Semiconductor Corp.
英文描述: 100-MHz PentiumII Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs(應(yīng)用于移動(dòng)PC機(jī)并帶有寬頻譜的100MHz奔騰II時(shí)鐘合成器/驅(qū)動(dòng)器)
中文描述: 100兆赫PentiumII時(shí)鐘合成器/驅(qū)動(dòng)器,帶有擴(kuò)頻移動(dòng)PC(應(yīng)用于移動(dòng)電腦機(jī)并帶有寬頻譜的100MHz的奔騰二時(shí)鐘合成器/驅(qū)動(dòng)器)
文件頁(yè)數(shù): 3/9頁(yè)
文件大?。?/td> 120K
代理商: CY2285
CY2285
3
Pin Summary: CY2285-2
Name
V
DD
V
DDCPU
V
SS
XTALIN
[3]
XTALOUT
[3]
PCI_STOP
CPU_STOP
PWR_DWN
DIV4
Pins
8, 13, 19, 28
25
7, 15, 21, 22
2
3
20
18
17
16
Description
3.3V Power supply
2.5V Power supply
Ground
Reference crystal input
Reference crystal feedback
Active LOW control input to stop PCI clocks
Active LOW control input to stop CPU clocks
Active LOW control input to power down device
Active LOW control input to enable divide-by-four option on
CPU and PCI clocks
2.5V CPU clock outputs
3.3V PCI clock outputs
3.3V Free-running PCI clock output
3.3V Early PCI clock output (Not Free-running)
3.3V 14.318-MHz reference clock output
3.3V 14.318-MHz reference clock output
3.3V 48-MHz USB clock output or select input and frequency
select strap option (use 10-k
external strap resistor)
Strap LOW = 66.6-MHz CPU Frequency
Strap HIGH = 100-MHz CPU Frequency
Active LOW control input to enable Spread Spectrum
CPUCLK[0:1]
PCICLK[1:5]
PCICLK_F
EPCICLK
REF0
REF1
USBCLK/SEL100/66
23, 24
5, 6, 9, 10, 11
4
12
1
27
14
SPREAD
26
Actual Clock Frequency Values
Clock Output
Target Frequency
(MHz)
Actual Frequency
(MHz)
PPM
CPUCLK
66.67
66.654
-240
CPUCLK
100
99.77
-2300
Power Management Logic
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
PCICLK
PCICLK_F
Other
Clocks
Osc.
PLLs
X
X
0
Low
Low
Low
Low
Off
Off
0
0
1
Low
Low
Running
Running
Running
Running
0
1
1
Low
Running
Running
Running
Running
Running
1
0
1
Running
Low
Running
Running
Running
Running
1
1
1
Running
Running
Running
Running
Running
Running
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參數(shù)描述
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