參數(shù)資料
型號(hào): CY2285
廠商: Cypress Semiconductor Corp.
英文描述: 100-MHz PentiumII Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs(應(yīng)用于移動(dòng)PC機(jī)并帶有寬頻譜的100MHz奔騰II時(shí)鐘合成器/驅(qū)動(dòng)器)
中文描述: 100兆赫PentiumII時(shí)鐘合成器/驅(qū)動(dòng)器,帶有擴(kuò)頻移動(dòng)PC(應(yīng)用于移動(dòng)電腦機(jī)并帶有寬頻譜的100MHz的奔騰二時(shí)鐘合成器/驅(qū)動(dòng)器)
文件頁數(shù): 2/9頁
文件大小: 120K
代理商: CY2285
CY2285
2
Pin Summary: CY2285-1, CY2285-3
Name
Pins
Description
V
DD
V
DDCPU
V
SS
XTALIN
[3]
XTALOUT
[3]
8, 12, 19, 28
3.3V Power supply voltage
25
2.5V Power supply for CPU clocks
1, 7, 15, 21, 22
Ground
2
Reference crystal input
3
Reference crystal feedback
PCI_STOP
20
Active LOW control input to stop PCI clocks
CPU_STOP
18
Active LOW control input to stop CPU clocks
PWR_DWN
17
Active LOW control input to power down device
SEL100
16
Select for enabling 100-MHz or 66-MHz CPU clock
HIGH = 100 MHz, LOW = 66 MHz
CPUCLK[0:1]
23, 24
2.5V CPU clock outputs
PCICLK[1:5]
5, 6, 9, 10, 11
3.3V PCI clock outputs
PCICLK_F
4
3.3V Free-running PCI clock output
REF0/SPREAD
26 (-1 option)
3.3V 14.318-MHz reference clock output and power-on spread spectrum
enable strap option.
Strap LOW = Spread Sprectrum enable
Strap HIGH = Spread Spectrum disable
SPREAD
26 (-3 option)
Active LOW control input to enable spread spectrum
REF1/SEL48
27
3.3V 14.318-MHz reference clock output and power-on 48-/24-MHz se-
lect strap option.
Strap LOW = 48 MHz on pin14
Strap HIGH = 24 MHz on pin14
USBCLK
13
3.3V 48-MHz USB clock output
USB_IOCLK/TS
14
3.3V 48-MHz or 24-MHz output and three-state strapping option.
Strap LOW = Enter three-state mode for testing
Strap HIGH = Normal Operation
Note:
3.
For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF.
PWRDWN
SEL100
V
SS48
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
15
SSOP
Top View
13
14
25
24
23
22
21
20
17
18
19
28
27
26
C
V
SSREF
XTAL_IN
XTAL_OUT
PCICLK_F
PCICLK1
PCICLK2
V
SSPCI
V
DDPCI
PCICLK3
PCICLK4
PCICLK5
V
DD48
USBCLK
USB_IOCLK/TS
REF1/SEL48
REF0/SPREAD
V
DDCPU
CPUCLK0
CPUCLK1
V
SSCPU
V
SSCORE
PCI_STOP
V
DDCORE
CPU_STOP
V
DDREF
PWRDWN
DIV4
V
SS48
1
2
3
4
5
6
7
8
9
10
11
12
16
15
SSOP
Top View
13
14
25
24
23
22
21
20
17
18
19
28
27
26
C
REF0
XTAL_IN
XTAL_OUT
PCICLK_F
PCICLK1
PCICLK2
V
SSPCI
V
DDPCI
PCICLK3
PCICLK4
PCICLK5
EPCICLK
V
DD48
USBCLK/SEL100/66
REF1
SPREAD
V
DDCPU
CPUCLK0
CPUCLK1
V
SSCPU
V
SSCORE
PCI_STOP
V
DDCORE
CPU_STOP
V
DDREF
PWRDWN
SEL100
V
SS48
1
2
3
4
5
6
7
8
9
10
11
12
16
15
SSOP
Top View
13
14
25
24
23
22
21
20
17
18
19
28
27
26
C
V
SSREF
XTAL_IN
XTAL_OUT
PCICLK_F
PCICLK1
PCICLK2
V
SSPCI
V
DDPCI
PCICLK3
PCICLK4
PCICLK5
V
DD48
USBCLK
USB_IOCLK/TS
REF1/SEL48
SPREAD
V
DDCPU
CPUCLK0
CPUCLK1
V
SSCPU
V
SSCORE
PCI_STOP
V
DDCORE
CPU_STOP
V
DDREF
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