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參數(shù)資料
| 型號： | CY2277APVI-12 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Circular Connector; No. of Contacts:56; Series:MS27656; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 206K |
| 代理商： | CY2277APVI-12 |
CY2277A
Document #: 38-07332 Rev. *A
Page 13 of 19
Timing Requirement for the SMBus
Parameter
t
10
t
11
t
12
t
13
t
14
t
15
t
16
Description
Min.
0
4.7
4
4.7
4
4.7
Max.
100
Unit
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
SCLK Clock Frequency
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated.
The LOW period of the clock.
The HIGH period of the clock.
Setup time for start condition. (Only relevant for a repeated start condition.)
Hold time DATA
for CBUS compatible masters.
for SMBus devices
DATA input set-up time
Rise time of both SDATA and SCLK inputs
Fall time of both SDATA and SCLK inputs
Set-up time for stop condition
5
0
t
17
t
18
t
19
t
20
Switching Waveforms
250
ns
μ
s
ns
μ
s
1
300
4.0
Duty Cycle Timing
t
1A
t
1B
CPUCLK Outputs HIGH/LOW Time
OUTPUT
V
DD
0V
t
1C
t
1D
All Outputs Rise/Fall Time
OUTPUT
t
2
t
3
V
DD
0V
t
2
t
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2277APVI-12T | 制造商:Cypress Semiconductor 功能描述: |
| CY2277PAC1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| CY2277PVC-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| CY2278A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY2278APAC-1L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
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