參數(shù)資料
型號(hào)： CY2277APVI-12
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Circular Connector; No. of Contacts:56; Series:MS27656; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No
中文描述： 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁(yè)數(shù)： 1/19頁(yè)
文件大?。?/td> 206K
代理商： CY2277APVI-12
Pentium
/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel
82430TX and 2 DIMMs or 3 SO-DIMMs
CY2277A
Cypress Semiconductor Corporation
Document #: 38-07332 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 7, 2002
408-943-2600
7A
Features
Mixed 2.5V and 3.3V operation
Complete clock solution to meet requirements of Pen-
tium
, Pentium
II, 6x86, or K6 motherboards
—
Four CPU clocks at 2.5V or 3.3V
—
Up to eight 3.3V SDRAM clocks
—
Seven 3.3V synchronous PCI clocks, one free
running
—
Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
—
One 2.5V IOAPIC clock at 14.318 MHz
—
Two 3.3V Ref. clocks at 14.318 MHz
Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
Factory-EPROM programmable output drive and slew
rate for EMI customization
MODE Enable pin for CPU_STOP and PCI_STOP
SMBus serial configuration interface
Available in space-saving 48-pin SSOP and TSSOP
packages.
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-
tium II, 6X86, and K6 portable PCs designed with the Intel
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
Logic Block Diagram
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip,
enabling
glitch-free
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2277A Selector Guide
transitions.
When
the
Note:
1.
One free-running PCI clock.
Clock Outputs
CPU (60, 66.6 MHz)
CPU (33.3, 66.6 MHz)
CPU (SMBus select-
able)
PCI (CPU/2)
SDRAM
USB/IO (48 or 24 MHz)
IOAPIC (14.318 MHz)
Ref (14.318 MHz)
CPU-PCI delay
-1/-1M
4
--
--
-3
--
4
--
-7M
4
--
--
-12/
-12M/
-12I
4
--
--
7
[1]
6/8
2
1
2
7
[1]
6/8
2
1
2
7
[1]
6/8
2
1
2
<1 ns
7
[1]
6/8
2
1
2
1
–
6 ns
1
–
6 ns
1
–
4 ns
EPROM
PinConfiguration
SSOP
Top View
XTALOUT
XTALIN
IOAPIC (14.318 MHz)
V
DDQ2
REF [0
–
1]
(14.318)
MHz
OSC.
SDRAM[0
–
5]
SEL
SDRAM7/PCI_STOP
CPU
PLL
MODE
SYS
PLL
/2
Delay
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33
32
31
30
29
28
25
26
27
36
35
34
REF1
REF0
V
SS
XTALIN
XTALOUT
MODE
V
DDQ3
PCICLK_F
PCICLK0
45
44
43
42
41
40
37
38
39
48
47
46
C
V
SS
PCICLK1
PCICLK2
PCICLK3
PCICLK4
V
DDQ3
PCICLK5
V
SS
SEL
SDATA
SCLK
V
DDQ3
USBCLK/IOCLK
USBCLK/IOCLK
V
SS
AV
DD
PWR_SEL
V
IOAPIC
PWR_DWN
V
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SDRAM0
SDRAM1
V
SDRAM2
SDRAM3
V
SS
SDRAM4
SDRAM5
V
DDQ3
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
AV
DD
SCLK
SDATA
CPUCLK[0
–
3]
V
DDCPU
SDRAM6/CPU_STOP
PCI[0
–
5]
PCICLK_F
USBCLK/IOCLK[0:1]
STOP
STOP
LOGIC
INTERFACE
CONTROL
LOGIC
SERIAL
Divide and
Mux Logic
PWR_DWN
相關(guān)PDF資料
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