參數(shù)資料
型號(hào)： CY2277APVC-1
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： LJT 128C 128#22D SKT RECP
中文描述： 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁(yè)數(shù)： 9/19頁(yè)
文件大?。?/td> 206K
代理商： CY2277APVC-1
CY2277A
Document #: 38-07332 Rev. *A
Page 9 of 19
Switching Characteristics (-1, -3)
[9, 10, 11]
Parameter
Output
t
1
CPUCLK
SDRAM
USBCLK
IOCLK
REF [0,1]
IOAPIC
t
1
PCI
t
2
CPUCLK,
IOAPIC
Description
Test Conditions
Min.
45
Typ.
50
Max.
55
Unit
%
Output Duty Cycle
[12]
t
1
= t
1A
÷
t
1B
Output Duty Cycle
[12]
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
PCI Clock Rising and
Falling Edge Rate
USB, I/O, REF0 Clock
Rising and Falling Edge
Rate
SDRAM Rising and Fall-
ing Edge Rate
REF1 Rising and Falling
Edge Rate
CPU Clock Rise Time
t
1
= t
1A
÷
t
1B
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 0.4V and 2.4V, V
DDCPU
= 3.3V
CPU clocks at 66.66 MHz
Between 0.4V and 2.4V, V
DDCPU
= 3.3V
40
0.75
0.75
50
55
4.0
4.0
%
V/ns
t
2
PCI
0.75
4.0
V/ns
t
2
USBCLK,
IOCLK,
REF0
SDRAM
Between 0.4V and 2.4V
0.8
4.0
V/ns
t
2
Between 0.4V and 2.4V
SDRAM clocks at 66.66 MHz
Between 0.4V and 2.4V
1.0
4.0
V/ns
t
2
REF1
0.5
2.0
V/ns
t
3
CPUCLK
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 0.4V and 2.4V, V
DDCPU
= 3.3V
Between 0.4V and 2.4V
0.4
0.5
2.13
2.0
2.5
ns
t
3
USBCLK,
IOCLK
CPUCLK
USB Clock and I/O Clock
Rise Time
CPU Clock Fall Time
ns
t
4
Between 2.0V and 0.4V, V
DDCPU
= 2.5V
Between 2.4V and 0.4V, V
DDCPU
= 3.3V
Between 2.4V and 0.4V
0.4
0.5
2.13
2.0
2.5
ns
t
4
USBCLK,
IOCLK
CPUCLK
CPUCLK,
PCICLK
CPUCLK,
SDRAM
CPUCLK
USB Clock and I/O Clock
Fall Time
CPU-CPU Clock Skew
CPU-PCI Clock Skew
(-1, -3)
CPU-SDRAM Clock
Skew
Cycle-Cycle Clock Jitter
ns
t
5
t
6
Measured at 1.25V, V
DDCPU
= 2.5V
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, V
DDCPU
= 2.5V
Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
Measured at 1.5V for 3.3V clocks
Measured at 1.5V
Measured at 1.5V
100
2.0
400
6.0
ps
ns
1.0
t
7
775
ps
t
8
450
ps
t
8
t
8
t
8
SDRAM
PCICLK
USBCLK,
IOCLK
CPUCLK,
PCICLK,
SDRAM
CPU, PCI,
SDRAM
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
650
500
1.3
ps
ps
ns
t
9
Power-up Time
CPU, PCI, and SDRAM clock stabiliza-
tion from power-up
3
ms
t
10
Frequency Slew Rate
Rate of change of frequency
2
MHz/
ms
Notes:
9.
10. All parameters specified with loaded outputs.
11.
Parameters specified with: V
= 2.5V, V
= 2.5V, V
DDQ3
= 3.3V.
12. Duty cycle is measured at 1.5V when V
DD
= 3.3V. When V
DDCPU
= 2.5V, CPUCLK duty cycle is measured at 1.25V.
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