參數(shù)資料
型號： CY2277APVC-1
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： LJT 128C 128#22D SKT RECP
中文描述： 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁數(shù)： 5/19頁
文件大?。?/td> 206K
代理商： CY2277APVC-1
CY2277A
Document #: 38-07332 Rev. *A
Page 5 of 19
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage..................................................
–
0.5 to +7.0V
Input Voltage............................................
–
0.5V to V
DD
+ 0.5
Storage Temperature (Non-Condensing)....
–
65
°
C to +150
°
C
Junction Temperature............................................... +150
°
C
Package Power Dissipation.............................................. 1W
Static Discharge Voltage............................................>2000V
(per MIL-STD-883, Method 3015, like V
DD
pins tied together)
Byte 1: CPU, 24/48 MHz Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
23
22
--
N/A
38
39
41
42
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
48/24 MHz (Active/Inactive)
48/24 MHz (Active/Inactive)
(Reserved) drive to
‘
0
’
Not Used, drive 0
CPUCLK3 (Active/Inactive)
CPUCLK2 (Active/Inactive)
CPUCLK1 (Active/Inactive)
CPUCLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
26
27
29
30
32
33
35
36
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Byte 5: Peripheral Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
--
--
--
45
--
--
1
2
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Reserved) drive to
‘
0
’
(Reserved) drive to
‘
0
’
(Reserved) drive to
‘
0
’
IOAPIC (Active/Inactive)
(Reserved) drive to
‘
0
’
(Reserved) drive to
‘
0
’
REF1 (Active/Inactive)
REF0 (Active/Inactive)
Byte 2: PCI Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
--
8
16
14
13
12
11
9
(Reserved) drive to
‘
0
’
PCICLK_F (Active/Inactive)
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
PCICLK0 (Active/Inactive)
Byte 4: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not used, drive to
‘
0
’
Not used, drive to
‘
0
’
Not used, drive to
‘
0
’
Not used, drive to
‘
0
’
Not used, drive to
‘
0
’
Not used, drive to
‘
0
’
Not used, drive to
‘
0
’
Not used, drive to
‘
0
’
Byte 6: Reserved, for future use
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