參數(shù)資料
型號(hào): CY2277APVC-12
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: LJT 37C 37#16 PIN RECP
中文描述: 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁數(shù): 4/19頁
文件大?。?/td> 206K
代理商: CY2277APVC-12
CY2277A
Document #: 38-07332 Rev. *A
Page 4 of 19
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to
0
.
SMBus Address for the CY2277A is:
Power Management Logic
CPU_STOP
X
PCI_STOP
X
PWR_DWN
0
CPUCLK
LOW
PCICLK
LOW
PCICLK_F
Stopped
Other Clocks
Stopped
Osc.
Off
PLLs
Off
0
0
1
LOW
LOW
Running
Running
Running
Running
0
1
1
LOW
33/30 MHz
Running
Running
Running
Running
1
0
1
66/60 MHz
LOW
Running
Running
Running
Running
1
1
1
66/60 MHz
33/30 MHz
Running
Running
Running
Running
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Bit 7 --
Bit 6 --
Pin #
Description
(Reserved) drive to
0
(Reserved) drive to
0
on -1, -1M, -3, -7M, -12,
-12M, -12I
(Reserved) drive to
0
on -1, -1M, -3, -7M, -12,
-12M, -12I
(Reserved) drive to
0
on -1, -1M, -3, -7M, -12,
-12M, -12I
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 1
1
1
0
0
0 - Normal Operation
Bit 5 --
Bit 4 --
Bit 3 23
Bit 2 22
Bit 1
Bit 0
--
Bit 0
1 - Three-State (see table below)
0 - N/A
1 - Test Mode (see table below)
Select Functions
Functional Description
Three-State
Test Mode
Outputs
CPU
PCI, PCI_F
Hi-Z
TCLK/4
SDRAM
Hi-Z
TCLK/2
Ref
IOAPIC
Hi-Z
TCLK
IOCLK
Hi-Z
TCLK/4
USBCLK
Hi-Z
TCLK/2
Hi-Z
TCLK/2
[5]
Hi-Z
TCLK
Note:
5.
TCLK supplied on the XTALIN, PIN 4.
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