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參數(shù)資料
| 型號(hào)： | CY2077SI-XXX |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器|?？苵 8引腳|塑料 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 305K |
| 代理商： | CY2077SI-XXX |
CY2077
7
Notes:
4.
5.
In synchronous mode the power-down or output three-state is not initiated until the next falling edge of the output clock.
In asynchronous mode the power-down or output three-state occurs within 25 ns irrespective of position in the ouput clock cycle.
Switching Waveforms
(continued)
Output Rise/Fall Time
OUTPUT
t
2
V
DD
0V
t
3
Power Down Timing
(synchronous and asynchronous modes)
V
DD
POWER
DOWN
0V
CLKOUT
t
4
1/f
t
5a
V
IL
V
IH
1/f
t
5b
CLKOUT
T
(synchronous
[4
]
)
(asynchronous
]
)
Power Up Timing
CLKOUT
V
DD
t
6
1/f
V
DD
-10%
POWER
UP
0V
min 2 ns
CLKOUT
(synchronous
[4
]
)
V
DD
OUTPUT
ENABLE
0V
Output Enable Timing
(synchronous and asynchronous modes)
V
IL
t
7a
t
8
High Impedance
CLKOUT
t
7b
t
8
High Impedance
T
(asynchronous
[5
]
)
V
IH
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