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參數(shù)資料
| 型號(hào)： | CY2077SI-XXX |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器|?？苵 8引腳|塑料 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 305K |
| 代理商： | CY2077SI-XXX |
CY2077
2
Functional Description
The CY2077 is an EPROM-programmable, high-accuracy,
general purpose, PLL-based design for use in applications
such as modems, disk drives, CD-ROM drives, video CD play-
ers, DVD players, games, set-top boxes, and data/telecommu-
nications.
The CY2077 can generate a clock output up to 133 MHz at 5V
or 100 MHz at 3.3V. It has been designed to give the customer
a very accurate and stable clock frequency with little to zero
PPM error. The CY2077 contains a 12-bit feedback counter
divider and 10-bit reference counter divider to obtain a very
high resolution to meet the needs of stringent design specifi-
cations. Further more, there are 8 output divide options of /1,
/2, /4, /8, /16, /32, /64, and /128. The output divider can select
between the PLL and crystal oscillator output/external clock,
providing a total of 16 different options. To add more flexibility
in designs. TTL or CMOS duty cycles can be selected.
Power management with the CY2077 is also very flexible. The
user may choose either a PWR_DWN or an OE feature with
which both have integrated pull-up resistors. PWR_DWN and
OE signals can be programmed to have asynchronous and
synchronous timing with respect to the output siginal. There is
a weak pull-down on the output that will pull CLKOUT low when
either the PWR_DWN or OE siginal is active. This weak
pull-down can easily be overridden by another clock signal in
designs where multiple clock signals share a signal path.
Multiple options for output selection, better power distribution
layout, and controlled rise and fall times enable the CY2077 to
be used in applications which require low jitter and accurate
reference frequencies.
EPROM Configuration Block
Table 1
summarizes the features which are configurable by
EPROM
.
Table 1. EPROM Adjustable Features
PLL Output Frequency
The CY2077 contains a high resolution PLL with 12 bit multi-
plier and 10 bit divider.The output frequency of the PLL is de-
termined by the following formula:
where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.
The calculation of P and Q values for a given PLL output fre-
quency is handled by the CyClocks software. Refer to the
“Custom Configuration Request Procedure” section for details.
Power Management Features
PWR_DWN and OE options are configurable by EPROM pro-
gramming for the CY2077. In PWR_DWN mode, all active cir-
cuits are powered down when the control pin is set to LOW.
When the control pin is set back to HIGH, both the PLL and
oscillator circuit must re-lock. In the case of OE, the output is
three-stated and weakly pulled down when the control pin is
set to LOW. The oscillator and PLL are still active in this state,
which leads to a quick clock output return when the control pin
is set back to HIGH.
Additionally, PWR_DWN and OE can be configured to occur
asynchronously or synchronously with respect to CLKOUT. In
asynchronous mode, PWR_DWN or OE disables CLKOUT im-
mediately (allowing for logic delays), without respect to the cur-
rent state of CLKOUT. Synchronous mode will prevent output
glitches by waiting for the next falling edge of CLKOUT after
PWR_DWN or OE becomes asserted. In either asynchronous
or synchronous setting, the output is always enabled synchro-
nously by waiting for the next falling edge of CLKOUT.
EPROM Adjustable Features
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing
(synchronous or asynchronous)
Adjust
Freq.
F
PLL
2
P
+
5
)
+
2
(
)
(
Q
F
REF
=
Pin Summary
Name
V
DD
V
SS
X
D
X
G
PWR_DWN / OE 4
CLKOUT
Pin
1
5,6,7
2
3
Description
Voltage supply.
Ground (all the pins have to be grounded).
Crystal output (leave this pin floating when external reference is used.).
Crystal input or external input reference.
EPROM programmable power down or output enable pin. Weak pull-up.
Clock output. Weak pull-down.
8
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