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參數(shù)資料
| 型號： | CY2077SI-XXX |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| 中文描述： | 雜項時鐘發(fā)生器|?？苵 8引腳|塑料 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 305K |
| 代理商： | CY2077SI-XXX |
CY2077
4
Output Clock Switching Characteristics Commercial
Over the Operating Range
[2]
Parameter
Description
t
1w
Output Duty Cycle at
1.4V, V
DD
= 4.5–5.5V
t
1w
= t
1A
÷
t
1B
125–133 MHz, C
L
<= 15 pF
t
1x
Output Duty Cycle at
V
DD
/2, V
DD
= 4.5–5.5V
t
1x
= t
1A
÷
t
1B
125–133 MHz, C
L
<= 15 pF
t
1y
Output Duty Cycle at
V
DD
/2, V
DD
= 3.0–3.6V
t
1y
= t
1A
÷
t
1B
t
2
Output Clock Rise Time
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 50 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 25 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 15 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 4.5V–5.5V, C
L
= 50 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 30 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 15 pF
t
3
Output Clock Fall Time
Between 0.8V–2.0V, V
DD
= 4.5V–5.5V, C
L
= 50 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 25 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 15 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 4.5V-5.5V, C
L
= 50 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 30 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 15 pF
t
4
Start-Up Time Out of
Power-Down
t
5a
Power Down Delay Time
(synchronous setting)
(T=period of output clk)
t
5b
Power Down Delay Time
(asynchronous setting)
t
6
Power Up Time
t
7a
Output Disable Time
(synchronous setting)
(T=period of output clk)
t
7b
Output Disable Time
(asynchronous setting)
t
8
Output Enable Time
(always synchronous
enable)
t
9
Peak-to-Peak Period
Jitter
V
DD
= 3.0V–5.5V, Fo <33 MHz
Test Conditions
Min.
45
45
45
45
45
45
45
40
Typ.
Max.
55
55
55
55
55
55
55
60
Unit
%
%
%
%
%
%
%
%
1–40 MHz, C
L
<= 50 pF
40–125 MHz, C
L
<= 25 pF
1–40 MHz, C
L
<= 50 pF
40–125 MHz, C
L
<= 25 pF
1–40 MHz, C
L
<= 30 pF
40–100 MHz, C
L
<= 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
1.8
1.2
0.9
3.4
4.0
2.4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
PWR_DWN pin LOW to HIGH
[3]
1
PWR_DWN pin LOW to output LOW
T/2
T+10
ns
PWR_DWN pin LOW to output LOW
10
15
ns
From power-on
[1]
OE pin LOW to output Hi-Z
1
2
ms
ns
T/2
T+10
OE pin LOW to output Hi-Z
10
15
ns
OE pin LOW to HIGH
(T=period of output clk)
T
1.5T
+25n
s
150
1%
ns
V
DD
=3.0V–3.6V, 4.5V–5.5V, Fo>33 MHz, VCO>100 MHz
80
0.3
%
ps
% of
F
O
Notes:
2.
3.
Not all parameters measured in production testing.
Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70
.
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