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參數(shù)資料
| 型號： | CY2071ASXL-XXX |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Single-PLL General-Purpose EPROM Programmable Clock Generator |
| 中文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, LEAD FREE, MS-012, SOIC-8 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 223K |
| 代理商： | CY2071ASXL-XXX |
CY2071A
Document #: 38-07139 Rev. *D
Page 4 of 9
Electrical Characteristics, Industrial 5.0V:
V
DD
= 5.0V ±10%, T
A
= –40°C to 85°C
[8]
Parameter
Description
V
OH
HIGH-Level Output Voltage
I
OH
= –4.0 mA
V
OL
LOW-Level Output Voltage
I
OL
= 4.0 mA
V
IH
Except Crystal Pins
V
IL
Except Crystal Pins
I
IH
Input HIGH Current
V
IN
= V
DD
– 0.5V
I
IL
Input LOW Current
V
IN
= 0.5V
I
OZ
Output Leakage Current
Three State Outputs
I
DD
V
DD
= V
DD
max. 5V operation, C
L
= 25 pF
Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
V
V
μ
A
μ
A
μ
A
mA
0.4
HIGH-Level Input Voltage
[9]
LOW-Level Output Voltage
[9]
2.0
0.8
10
150
250
75
V
DD
Supply Current
[10]
40
Electrical Characteristics, Industrial 3.3V
V
DD
=3.3V ±10%, T
A
= –40°C to +85°C
[8]
Parameter
Description
V
OH
HIGH-Level Output Voltage
I
OH
= –4.0 mA
V
OL
LOW-Level Output Voltage
I
OL
= 4.0 mA
V
IH
Except Crystal Pins
V
IL
Except Crystal Pins
I
IH
Input HIGH Current
V
IN
= V
DD
– 0.5V
I
IL
Input LOW Current
V
IN
= 0.5V
I
OZ
Output Leakage Current
Three State Outputs
I
DD
V
DD
= V
DD
max. 3.3V operation,
C
L
=
15 pF
Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
V
V
μ
A
μ
A
μ
A
mA
0.4
HIGH-Level Input Voltage
[9]
LOW-Level Output Voltage
[9]
2.0
0.8
10
150
250
50
V
DD
Supply Current
[10]
24
Notes:
11. Guaranteed by design, not 100% tested.
12.When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF.
13.Reference Output duty cycle depends on XTALIN duty cycle.
14.Measured at 1.4V.
Switching Characteristics, Commercial 5.0V
[11]
Parameter
t
1
Name
Description
Min.
7.692
[130 MHz]
10
[100 MHz]
Typ.
Max.
2000
[500 kHz]
2000
[500 kHz]
1
Unit
ns
Output Period
Clock output range 5V
operation 25-pF load
CY2071A
CY2071AF
ns
t
1A
Clock Jitter
Peak-to-peak period jitter (t
1
max. – t
1
min.),
% of clock period, f
OUT
≤
16 MHz
Peak-to-peak period jitter
(16 MHz
≤
f
OUT
≤
50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Duty cycle
[13, 14]
for outputs, (t
2
÷
t
1
)
f
OUT
≤
60 MHz
0.8
%
t
1B
Clock Jitter
350
500
ps
t
1C
Clock Jitter
[12]
Output Duty Cycle
250
50%
350
55%
ps
45%
Output Duty Cycle
[12]
Duty cycle
[14]
for outputs, (t
2
÷
t
1
),
f
OUT
> 60 MHz
Rise Time
[12]
Output clock rise time
Fall Time
[12]
Output clock fall time
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
40%
50%
60%
t
3
t
4
t
5
1.5
1.5
2.5
2.5
0.5
ns
ns
ns
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