參數(shù)資料
型號: CY2210
廠商: Cypress Semiconductor Corp.
英文描述: 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support(由AGP,USB和DRCG支持的133MHz寬頻譜時鐘合成器/驅(qū)動器)
中文描述: 133 - MHz的擴頻時鐘合成器/驅(qū)動器的AGP,USB和DRCG支持(由采購協(xié)定時的USB和DRCG支持的133MHz的寬頻譜時鐘合成器/驅(qū)動器)
文件頁數(shù): 1/9頁
文件大?。?/td> 129K
代理商: CY2210
133-MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
CY2210
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 6, 2000, rev. **
Features
Benefits
Mixed 2.5V and 3.3V Operation
Compliant to Intel CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
Multiple output clocks at different frequencies
—Four CPU clocks, up to 133 MHz
—Eight synchronous PCI clocks, 1 free-running
—Two CPU/2 clocks, at one-half the CPU frequency
—Four AGP clocks at 66 MHz
—Three synchronous APIC clocks, at 16.67 MHz
—One USB clock at 48 MHz
—Two reference clocks at 14.318 MHz
Spread Spectrum clocking
—32.5-kHz modulation frequency @ 133 MHz
—33.1-kHz modulation frequency @ 100 MHz
—EPROM programmable percentage of spreading.
Default is –0.6%, which is recommended by Intel
Power-down features
Three Select inputs
Low-skew and low-jitter outputs
OE and Test Mode support
56-pin SSOP package
Logic Block Diagram
Usable with Pentium
II and Pentium
III processors
Single-chip main motherboard clock generator
—Driven together, support 4 CPUs and a chipset
—Support for 4 PCI slots and chipset
—Drives up to two main memory clock generators, includ-
ing DRCG (CPUCLK/2)
—Support for multiple AGP slots
—Support multiprocessing systems
—Supports USB frequencies and I/O chip
Enables reduction of EMI in some systems
Supports mobile systems
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
Widely available, standard package enables lower cost
Intel and Pentium are registered trademarks of Intel Corporation.
EPROM
XTALOUT
XTALIN
APICCLK [0–2] (16.67 MHz)
14.318
MHz
OSC.
PCICLK_F (33.33 MHz)
SEL1
SEL0
SEL133
SPREAD
CPU
PLL
REFCLK [0–1] (14.318 MHz)
CPUCLK [0–3]
PCICLK [1–7] (33.33 MHz)
SYS
PLL
USBCLK (48 MHz)
CPU_STOP
PCI_STOP
CPUCLK/2 [0–1] (DRCG)
Divider,
EPROM-Prog
Delay
and
Stop Logic
PWR_DWN
AGPCLK [0–3] (66.67 MHz)
SSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
33
32
31
30
29
36
35
34
V
SSREF
REFCLK0
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
45
44
43
42
41
37
38
39
40
48
47
46
REFCLK1
V
DDREF
XTALIN
XTALOUT
49
52
51
50
53
56
55
54
V
DDPCI
PCICLK2
PCICLK3
PCICLK6
PCICLK7
V
SSPCI
V
DDAGP
V
SSAGP
AGPCLK2
V
DDUSB
USBCLK
V
SSUSB
SPREAD
SEL1
V
SSCPU
AV
DD
V
DDCPU
CPUCLK3
APICCLK0
V
SSAPIC
V
SSPCI
PCICLK5
V
DDPCI
V
SSAGP
AGPCLK0
AGPCLK3
V
DDAGP
SEL133
PCI_STOP
V
DDCPU
CPUCLK1
CPUCLK/2
V
DDAPIC
APICCLK2
PCICLK_F
PCICLK1
V
SSPCI
PCICLK4
AGPCLK1
SEL0
PWR_DWN
CPU_STOP
AV
SS
CPUCLK0
V
SSCPU
CPUCLK2
V
SSCPU/2
CPUCLK/2
V
DDCPU/2
APICCLK1
C
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