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參數(shù)資料
| 型號(hào)： | CY2040WAF |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 94K |
| 代理商： | CY2040WAF |
CY2040WAF
PRELIMINARY
Document #: 38-07234 Rev. *A
Page 7 of 10
tj3
Period Jitter (Osc. output)
Period Jitter (PLL output)
10
–
30 MHz output directly from oscillator
Vdd = 4.5V to 5.5V, Fo > 33 MHz,
Fvco > 100 MHz, 10
–
30MHz input
[1]
Vdd = 2.7V to 3.6V, Fo > 33 MHz,
Fvco > 100 MHz, 10
–
30 MHz input
[1]
Vdd = 2.7V to 5.5V, 16 MHz < Fo < 33 MHz
10
–
30 MHz input
[1]
Vdd = 2.7V to 5.5V, 1 MHz < Fo < 16 MHz
10
–
30 MHz input
[1]
±125
±125
ps
ps
±75
±100
±200
ps
±300
ps
±500
ps
Other AC Characteristics
t
STP
Power-down delay time;
ASYNC
Power-down delay time;
SYNC
t
PU
Power-up time (Osc start-up
time)
t
PXZ
Output disable time; SYNC
Output disable time; ASYNC OE pin HIGH to LOW
T
PZX
Output enable time; SYNC
(always SYNC)
f
O
Output frequency
OE pin HIGH to LOW (T = output clock period)
10
25
ns
OE pin HIGH to LOW (T = output clock period)
T/2
T+25
ns
From power-on (min. Vbatt = 3.0V). Decided by
32.768-kHz crystal startup
OE pin HIGH to LOW (T = output clock period)
3
sec
T/2
10
T
T+25
25
1.5T+25
ns
ns
ns
OE pin LOW to HIGH (T = output clock period)
Out1 (Vbatt
= 2.5V to 3.6V)
Out2 (Vdd
= 2.7V to 5.5V)
Out3 (Vdd
= 2.7V to 5.5V)
Vdd
= 2.7V to 5.5V
32.768kHz
32.768kHz
Hz
1M
60
66M
133
F
PLL
Crystal oscillator 1 (32.768 kHz)
F
C
Crystal frequency
D
L
Crystal drive level
–
R
Negative resistance
Crystal oscillator 2 (10
–
30 MHz)
F
C
Crystal frequency
D
L
Crystal drive level
–
R
Negative resistance
PLL frequency
MHz
Out1
At 32.768 kHz, with ESR <= 55 k
At 32.768 kHz
32.768
0.1
–
200
kHz
μ
W
K
0.5
Out2, Out3
At 28 MHz, with ESR <= 20
At 10
–
30 MHz
10
30
150
MHz
μ
W
–
300
AC Characteristics
(T
J
=
–
10
°
C to 100
°
C unless otherwise noted) (continued)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Output Modes (Programmable)
[2]
Mode
1
2
3
4
5
6
Out2
Out3
32.768 kHz (Level Shifted)
32.768 kHz (Level Shifted)
32.768 kHz (Level Shifted)
PLL
PLL
PLL
10
–
30 MHz crystal output
10
–
30 MHz crystal output divided by 2
PLL
PLL
10
–
30 MHz crystal output
10
–
30 MHz crystal output divided by 2
Note:
1.
2.
Out2 and Out3 must be at the same frequency for jitter specs to be valid.
Refer to the
“
7C80400 Programming Specification
”
for details.
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