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參數(shù)資料
| 型號(hào)： | CY2040WAF |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 94K |
| 代理商： | CY2040WAF |
PRELIMINARY
Programmable Clock Die With
Precision 32-kHz Input
Benefits
Maximize value
Precision RTC; CPU clock (powerdown mode), DRAM refresh
User selectable output frequency
Output Enables for Out2 and Out3
CY2040WAF
Cypress Semiconductor Corporation
Document #: 38-07234 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 7, 2002
408-943-2600
2CY2040WAF
Features
3 Clock outputs
32.768 kHz
1 MHz–66 MHz output
Two Control inputs
Xd1
Xg1
PDOE2
OE1
LEVEL SHIFTERS + LATCH
Out1
PLL
(13 BIT P)
(7 BIT Q)
Out2
Out3
M
Logic Block Diagram
Xd2
Xg2
10-30MHz
OSC with
Trim Array
/2
EPROM Power-
save Circuit
Vbatt
Vdd
Vss
Vss
SHADED AREA - CIRCUITS RUNNING ON BATTERY
LEVEL SHIFT
7 BIT
POST
DIVIDER
Vpp
CONFIG
EPROM
Config Bits
from
EPROM
Power
On
Reset
OSC with
Trim
32.768KHz
Array
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