參數(shù)資料
型號: CXL5513P
廠商: Sony Corporation
英文描述: CMOS-CCD 1H Delay Line for NTSC
中文描述: CMOS與CCD延遲線上半年對NTSC
文件頁數(shù): 1/9頁
文件大小: 153K
代理商: CXL5513P
—1—
E93Y20-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Input Signal Amplitude
V
SIG
500 mVp-p (typ.), 572 mV
P-P
(max.)
Functions
680-bit CCD register
Clock driver
Auto bias circuit
Input center bias circuit.
Sample and hold circuit
Tripling PLL circuit
Inverted output
Structure
CMOS-CCD
Description
The CXL5513M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1 H delay time for NTSC chroma signals
including the external lowpass filter.
Features
Single 5 V power supply
Low power consumption
Built-in peripheral circuit
Built-in tripling PLL circuit
Center bias mode
Absolute Maximum Ratings
(Ta=25 °C)
Supply voltage
Operating temperature Topr
Storage temperature
Allowable power dissipation
V
DD
+6
V
–10 to +60
–55 to +150
°C
°C
Tstg
P
D
CXL5513M
CXL5513P
350
480
mW
mW
Recommended Operating Range
(Ta=25 C)
V
DD
5 V±5 %
Recommended Clock Conditions
(Ta=25 C)
Input clock amplitude
Clock frequency
Input clock waveform
V
CLK
f
CLK
Sine wave
400 mVp-p (Typ.)
3.579545 MHz
CMOS-CCD 1H Delay Line for NTSC
CXL5513M
8 pin SOP (Plastic)
CXL5513P
8 pin DIP (Plastic)
Block Diagram and Pin Configuration
(Top View)
V
SS
OUT
AB
IN
V
DD
CLK
VCO IN
CCD
(680bit)
VCO OUT
1
2
3
4
5
6
7
8
Auto-bias circuit
Bias circuit
Output circuit
(S/H 1 bit)
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
CXL5513M/P
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