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參數(shù)資料
| 型號(hào)： | CXL5520M |
| 廠商： | Sony Corporation |
| 英文描述： | CMOS-CCD Baseband 1H Delay Line |
| 中文描述： | CMOS與CCD氫基帶延遲線 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 120K |
| 代理商： | CXL5520M |
– 1 –
CXL5520M/P
E95X04-PS
CMOS-CCD Baseband 1H Delay Line
Description
CXL5520 is a CMOS-CCD baseband 1H delay line
designed for TV signal processing.
Features
Single 5V power supply
Low power consumption
Built-in line locked PLL circuit
Built-in 2 comb filters
(Addition of delayed and non-delayed output signal.)
Built-in peripheral circuits
Absolute Maximum Ratings
(Ta = 25°C)
Supply voltage
Operating temperature
Storage temperature
Allowable power dissipation
V
DD
Topr
Tstg
+6
V
–10 to +60
–55 to +150
°C
°C
P
D
CXL5520M 400
CXL5520P
mW
mW
800
Recommended Operating Condition
(Ta = 25°C)
Supply voltage
V
DD
5V ± 5%
Recommended Clock Condition
(Ta = 25°C)
Top pulse voltage
Frequency
Input clock waveform
V
CLK
f
CLK
Sandcastle pulse
3 to 7
15.625
V
kHz
Pin Description
Input Signal Amplitude
± (R-Y) PAL and NTSC Vsig
± (B-Y) PAL and NTSC
± (R-Y) SECAM
± (B-Y) SECAM
525 mVp-p (Typ.)
665 mVp-p (Typ.)
1.05 Vp-p
1.33 Vp-p
Vsig
Vsig
Vsig
(Typ.)
(Typ.)
Function
2 comb filters outputs
(Addition of delayed and non-delayed output signal.)
Timing generator and clock driver
Line Locked PLL circuit (Sandcastle pulse)
Autobias circuit
Pulse clamp circuit
Sample and hold circuit and output Amp.
Structure
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL5520M
16 pin SOP (Plastic)
CXL5520P
16 pin DIP (Plastic)
Pin
No.
1
2
3
4
5
6
7
8
V
DD
AB
(NC)
(NC)
SAND
VCO IN
(NC)
GND
+5V supply voltage
Autobias output
not connected
not connected
Sandcastle pulse input
VCO input
not connected
Ground
9
10
11
12
13
14
15
16
(NC)
(NC)
Vo (R-Y)
Vo (B-Y)
(NC)
Vi (B-Y)
(NC)
Vi (R-Y)
not connected
not connected
± (R-Y) output signal
± (B-Y) output signal
not connected
± (B-Y) input signal
not connected
± (R-Y) input signal
Symbol
Description
Pin
No.
Symbol
Description
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|---|---|
| CXL5520M/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-CCD Baseband 1H Delay Line |
| CXL5520P | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD Baseband 1H Delay Line |
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