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參數(shù)資料
| 型號： | CXL5512M |
| 廠商： | Sony Corporation |
| 英文描述： | CMOS-CCD 1H Delay Line for NTSC |
| 中文描述： | CMOS與CCD延遲線上半年對NTSC |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 158K |
| 代理商： | CXL5512M |
—1—
E93Y19-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Input Signal Amplitude
V
SIG
500mVp-p (typ.), 572 mVp-p (max.)
(at internal clamp condition)
Functions
680-bit CCD register
Clock driver
Auto-bias circuit
Sync tip clamp circuit
Sample and hold circuit
Tripling PLL circuit
Inverted output
Structure
CMOS-CCD
Description
The CXL5512M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for NTSC signals including
the external lowpass filter.
Features
Single 5 V power supply
Low power consumption
Built-in peripheral circuit
Built-in tripling PLL circuit
Sync tip clamp mode
Absolute Maximum Ratings
(Ta=25 °C)
Supply voltage
Operating temperature Topr
Storage temperature
Allowable power dissipation
V
DD
+6
V
–10 to +60
–55 to +150
°C
°C
Tstg
P
D
CXL5512M
CXL5512P
350
480
mW
mW
Recommended Operating Range
(Ta=25 C)
V
DD
5 V±5 %
Recommended Clock Conditions
(Ta=25 C)
Input clock amplitude
Clock frequency
Input clock waveform Sine wave
V
CLK
f
CLK
400mVp-p (Typ.)
3.579545
MHz
CMOS-CCD 1H Delay Line for NTSC
CXL5512M
8 pin SOP (Plastic)
CXL5512P
8 pin DIP (Plastic)
Block Diagram and Pin Configuration
V
SS
OUT
AB
IN
V
DD
CLK
VCO IN
CCD
(680bit)
1
2
3
4
5
6
7
8
Auto-bias circuit
Clamp circuit
Output circuit
(S/H 1 bit)
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
VCO OUT
CXL5512M/P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXL5512P | CMOS-CCD 1H Delay Line for NTSC |
| CXL5513M | CMOS-CCD 1H Delay Line for NTSC |
| CXL5513P | CMOS-CCD 1H Delay Line for NTSC |
| CXL5514M | CMOS-CCD 1H Delay Line for PAL |
| CXL5514P | CMOS-CCD 1H Delay Line for PAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXL5512M/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5512P | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5513M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5513M/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5513P | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD 1H Delay Line for NTSC |
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