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參數資料
| 型號： | CXD3412GA |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| 中文描述： | 時序發(fā)生器和幀讀出CCD圖像傳感器信號處理器 |
| 文件頁數： | 24/46頁 |
| 文件大?。?/td> | 383K |
| 代理商： | CXD3412GA |
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CXD3412GA
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3412GA and
control is applied immediately at the rising edge of SEN1.
See the Pin Status Table for the pin status in each mode.
D39
X
0
1
D38
0
1
1
Operating mode
Normal operating mode
Sleep mode
Standby mode
Symbol
CAM
SLP
STB
Control data: D36 , D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is 90
°
relative to MCKO.
D37
0
0
1
1
D36
0
1
0
1
Degree of adjustment (
°
)
0
90
180
270
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
0
0
1
1
D34
0
1
0
1
Waveform pattern
(Normal)
(Shifted rearward)
(Shifted forward)
(Wide)
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
0
1
Description of operation
Wide CLPOB generation OFF
Wide CLPOB generation ON
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