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參數(shù)資料
| 型號(hào)： | CXD3412GA |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| 中文描述： | 時(shí)序發(fā)生器和幀讀出CCD圖像傳感器信號(hào)處理器 |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 383K |
| 代理商： | CXD3412GA |
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–
15
–
CXD3412GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics
(Fc = 22.5MSPS, DV
DD1, 2
= AV
DD1, 2, 3, 4, 5
= 3.3V, Ta = 25
°
C)
Item
Supply voltage 1
Supply voltage 2
Supply voltage 3
Analog input
capacitance
Input voltage
A/D clock duty
Output voltage
Pins
DV
DD1
DV
DD2
AV
DD1
,
AV
DD2
,
AV
DD3
,
AV
DD4
,
AV
DD5
CCDIN
SCK2, SSI2,
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI,
CLPOBI,
CLPDMI, PBLKI
ADCLKI
D0 to D9
Symbol
V
DD
e
V
DD
f
V
DD
g
C
IN
V
I+
V
I
–
V
OH
V
OL
Conditions
Feed current where I
OH
=
–
2.0mA
Pull-in current where I
OL
= 2.0mA
Min.
3.0
3.0
3.0
V
DD
e
–
0.9
Typ.
3.3
3.3
3.3
15
1.8
1.1
50
Max.
3.6
3.6
3.6
0.4
Unit
V
V
V
pF
V
V
%
V
V
Analog Characteristics
(Fc = 22.5MSPS, DV
DD1, 2
= AV
DD1, 2, 3, 4, 5
= 3.3V, Ta = 25
°
C)
Item
CCDIN input voltage amplitude
PGA maximum gain
PGA minimum gain
ADC resolution
ADC maximum conversion rate
ADC integral non-linearity error
ADC differential non-linearity error
Signal-to-noise ratio
CCDIN input voltage clamp level
CCD optical black signal clamp
level
Symbol
V
IN
Gmax
Gmin
Fc max
E
L
E
D
SNR
CLP
OB
Conditions
PGA gain = 0dB, output full scale
PGA gain setting data = "3FFh"
PGA gain setting data = "000h"
PGA gain = 0dB
PGA gain = 0dB
CCDIN input connected to GND
via a coupling capacitor
PGA gain = 0dB
OBLVL = "8h"
PGA gain = 0dB
Min.
900
22.5
Typ.
42
–
6
10
±1.0
±0.5
77
1.5
32
Max.
1100
Unit
mV
dB
dB
bit
MHz
LSB
LSB
dB
V
LSB
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