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參數(shù)資料
| 型號(hào)： | CXD3048R |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo + Shock-proof Memory Controller + Digital High & Bass Boost |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服防震內(nèi)存控制器數(shù)字高 |
| 文件頁數(shù)： | 15/205頁 |
| 文件大?。?/td> | 1481K |
| 代理商： | CXD3048R |
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CXD3048R
Contents
[1] CPU Interface
§1-1. CPU Interface Timing...................................................................................................................... 16
§1-2. CPU Interface Command Table ...................................................................................................... 16
§1-3. CPU Command Presets ................................................................................................................. 32
§1-4. Description of SENS Signals .......................................................................................................... 43
§1-5. Description of Commands .............................................................................................................. 45
[2] Subcode Interface
§2-1. P to W Subcode Readout ............................................................................................................. 101
§2-2. 80-bit Subcode-Q Readout ........................................................................................................... 101
[3] Description of Modes
§3-1. CLV-N Mode .................................................................................................................................. 108
§3-2. CLV-W Mode ................................................................................................................................. 108
§3-3. CAV-W Mode................................................................................................................................. 108
§3-4. VCO-C Mode ................................................................................................................................ 109
[4] Description of Other Functions
§4-1. Channel Clock Recovery by Digital PLL Circuit ........................................................................... 112
§4-2. Frame Sync Protection ................................................................................................................. 114
§4-3. Error Correction ............................................................................................................................ 114
§4-4. DA Interface .................................................................................................................................. 115
§4-5. Digital Out ..................................................................................................................................... 118
§4-6. Servo Auto Sequence ................................................................................................................... 124
§4-7. Digital CLV .................................................................................................................................... 132
§4-8. CD-DSP Block Playback Speed ................................................................................................... 133
§4-9. Description of DAC Block and Shock-proof Memory Controller Block Circuits............................ 133
§4-10. DAC Block Input Timing ................................................................................................................ 134
§4-11. Description of DAC Block Functions............................................................................................. 135
§4-12. LPF Block...................................................................................................................................... 140
§4-13. Description of Shock-proof Memory Controller Block Functions.................................................. 141
§4-14. CPU to DRAM Access Function................................................................................................... 146
§4-15. Asymmetry Correction .................................................................................................................. 150
§4-16. CD TEXT Data Demodulation....................................................................................................... 151
[5] Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of Servo Signal Processing System ............................................................ 153
§5-2. Digital Servo Block Master Clock (MCK)...................................................................................... 154
§5-3. DC Offset Cancel [AVRG Measurement and Compensation] ...................................................... 155
§5-4. E:F Balance Adjustment Function ................................................................................................ 156
§5-5. FCS Bias Adjustment Function..................................................................................................... 156
§5-6. AGCNTL Function......................................................................................................................... 158
§5-7. FCS Servo and FCS Search ........................................................................................................ 160
§5-8. TRK and SLD Servo Control ........................................................................................................ 161
§5-9. MIRR and DFCT Signal Generation ............................................................................................. 162
§5-10. DFCT Countermeasure Circuit ..................................................................................................... 163
§5-11. Anti-shock Circuit .......................................................................................................................... 163
§5-12. Brake Circuit ................................................................................................................................. 164
§5-13. COUT Signal................................................................................................................................. 165
§5-14. Serial Readout Circuit................................................................................................................... 165
§5-15. Writing to Coefficient RAM ........................................................................................................... 166
§5-16. PWM Output ................................................................................................................................. 166
§5-17. Servo Status Changes Produced by LOCK Signal ...................................................................... 167
§5-18. Description of Commands and Data Sets .................................................................................... 167
§5-19. List of Servo Filter Coefficients..................................................................................................... 195
§5-20. Filter Composition ......................................................................................................................... 197
§5-21. TRACKING and FOCUS Frequency Response ........................................................................... 203
[6] Application Circuit
.................................................................................................................................. 204
Explanation of abbreviations
AVRG: Average
AGCNTL: Auto gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
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| CXD3141 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ccd-cmosIC資料 |
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