參數資料
型號: CXD3003
廠商: Sony Corporation
元件分類: 數字信號處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數字信號處理器,具有內置數字伺服和DAC
文件頁數: 111/137頁
文件大?。?/td> 1361K
代理商: CXD3003
– 111 –
CXD3003R
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KD7
KD6
KD5
KD4
KD3
KD2
KD1
KD0
When D15 = 0
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
1
FB9
FB8
FB7
FB6
FB5
FB4
FB3
FB2
FB1
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 1
FBIAS register write
FB9 to FB1: Data; FB9 is MSB two's complement data.
For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256
×
V
DD
/4 and
FB9 to FB1 = 100000000 to –256/256
×
V
DD
/4 respectively. (V
DD
: supply voltage)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
0
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
When D15 = D14 = D13 = D12 = D11 = 1 ($34F)
D10 = 0
FBIAS LIMIT register write
FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB.
When using the FBIAS register in counter mode, counter operation stops when the
value of FB9 to 1 matches with FBL9 to 1.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
0
TV9
TV8
TV7
TV6
TV5
TV4
TV3
TV2
TV1
TV0
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 0
TRVSC register write
TV9 to TV0: Data; TV9 is MSB two's complement data.
For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256
×
V
DD
/4
and TV9 to TV0 = 1100000000 to –256/256
×
V
DD
/4 respectively. (V
DD
: supply voltage)
Note)
When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to
each bit TV8 to TV0 during external write are read out.
When reading out internally measured values and then writing these values externally, set TV9 the
same as TV8.
$34
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