- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄378985 > CXD2728Q (Sony Corporation) Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞Pro邏輯解碼器) PDF資料下載
參數(shù)資料
| 型號(hào)： | CXD2728Q |
| 廠(chǎng)商： | Sony Corporation |
| 英文描述： | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞Pro邏輯解碼器) |
| 中文描述： | 單片杜比定向邏輯環(huán)繞聲解碼器（單片杜比環(huán)繞專(zhuān)業(yè)邏輯解碼器） |
| 文件頁(yè)數(shù)： | 57/61頁(yè) |
| 文件大小： | 467K |
| 代理商： | CXD2728Q |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)當(dāng)前第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)
– 57 –
CXD2728Q
0000H
58.0ms
9fe0H
a000H
tp_fb
ap0_in
92.8ms (0000H to ffe0H)
cfe0H
ap0_out
d000H
ap1_in
ffe0H
ap1_out
17.4ms
17.4ms
Fig. 8-5-3. Delay Time Setting Example (1/2 Decimation)
Note)
Assuming the tap read address to be 0000H, the comb filter has a delay time of "0". However, the all
pass filters are delayed by one sample after reading from the delay RAM.
Therefore, perfect through operation is not possible even if (write address) = (read address).
Table 8-5-12. SFC Mode Delay Time Setting Value Examples
(7)-2. All Pass Filters (APF0, APF1)
The all pass filter delay times are determined by (read address) – (write address - 0020H). Set ap
_in and
ap
_out so that this subtraction results in the target delay time setting value. The calculation method is the
same as that for tp_fb.
Example)
When setting a maximum comb filter delay time of 58ms and splitting the remainder evenly
between APF0 and APF1.
(1/2 decimation)
(ffe0h – 9fe0H)/2 = 3000H
3000H is used for each.
tp_fb = 9fe0H, so:
ap0_in = a000H, ap0_out = 9fe0H + 3000H = cfe0H
ap1_in = d000H, ap1_out = cfe0H + 3000H = ffe0H
0020H
0040H
·
·
3720H
·
6e40H
·
a560H
·
dc80H
·
ff80H
·
ffa0H
0.022ms
0.045ms
·
·
10.000ms
·
20.000ms
·
30.000ms
·
40.000ms
·
46.349ms
·
46.372ms
0.045ms
0.090ms
·
·
20.000ms
·
40.000ms
·
60.000ms
·
80.000ms
·
92.698ms
·
92.744ms
0.068ms
0.136ms
·
·
30.000ms
·
60.000ms
·
90.000ms
·
120.000ms
·
139.048ms
·
139.116ms
Setting
value
Delay (fs = 44.1kHz)
1/1 (No decimation)
1/2 decimation
1/3 decimation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD2930BR | GPS LSI With Built-In 32-Bit RISC CPU(全球定位系統(tǒng)（GPS）大規(guī)模集成電路(LSI)(內(nèi)置32位RISC中央處理器)) |
| CXD2931R | 1 Chip GPS LSI(單片全球定位系統(tǒng)（GPS）大規(guī)模集成電路LSI) |
| CXD2951GA-2 | Single Chip GPS LSI |
| CXD3000R | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD3005R | CD Digital Signal Processor with Built-in Digital Servo and DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2917 | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:DIGITAL AUDIO DATA MODULATION AND TRANSMISSION |
| CXD2917Q | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:DIGITAL AUDIO DATA MODULATION AND TRANSMISSION |
| CXD2930BR | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:GPS LSI with Built-in 32-bit RISC CPU |
| CXD2931GA-9 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:RF/BASEBAND CIRCUIT|CMOS|LGA|144PIN|CERAMIC |
| CXD2931R | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:1 chip GPS LSI |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。