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參數(shù)資料
| 型號(hào)： | CXD2728Q |
| 廠商： | Sony Corporation |
| 英文描述： | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞Pro邏輯解碼器) |
| 中文描述： | 單片杜比定向邏輯環(huán)繞聲解碼器（單片杜比環(huán)繞專業(yè)邏輯解碼器） |
| 文件頁數(shù)： | 18/61頁 |
| 文件大小： | 467K |
| 代理商： | CXD2728Q |
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– 18 –
CXD2728Q
(4) Details of Communication Methods
The definitions of signal timing required for control from the microcomputer are given below.
(4)-1. Signal Timing
First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to
the RVDT pin.
The address section data is 8 bits for both the coefficient RAM and setup register, and the setup register has a
length of one word, so optional data can be transferred. Address section data is sent with LSB first.
Mode section data is fixed at 8 bits regardless of the transfer contents.
The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following
restrictions:
RV data must be established before SCK rises (t
DS
≥
20ns).
RV data must be held for 1t + 20ns or more after SCK rises (t
DH
).
SCK itself has the following restrictions:
SCK Low level must be 1t + 20ns or more (t
SWL
).
SCK High level must be 1t + 20ns or more (t
SWH
).
After the SCK rise which corresponds to the mode section final data, XLAT rises (t
SLP
≥
20ns).
The XLAT Low level width must be maintained at 1t + 20ns or more (t
LWL
). The fall timing is restricted in that
even if REDY falls due to SCK during the preceding transfer, 3t + 20ns or more (t
SLD
) is required from the SCK
rise which corresponds to the data section final data.
Further, if preceding transfers have been performed and REDY = Low, XLAT must rise after REDY = High.
A0
A7
M0
M7
SQ00
SQ15
RVDT
SCK
XLAT
REDY
A0
M7
t
DH
t
DS
t
SWH
t
SWL
t
SLD
or t
LWH
t
LWL
t
RLP
t
LDR
t
LSD
t
SLP
t
BSP
t
SLP
t
LDR
t
RLP
t
SS
t
SLD
t
SBD
D0/SQ00
D15/SQ15
Fig. 5-2. Write Timing
t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)
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