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參數(shù)資料
| 型號： | CXD2728Q |
| 廠商： | Sony Corporation |
| 英文描述： | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞Pro邏輯解碼器) |
| 中文描述： | 單片杜比定向邏輯環(huán)繞聲解碼器（單片杜比環(huán)繞專業(yè)邏輯解碼器） |
| 文件頁數(shù)： | 32/61頁 |
| 文件大小： | 467K |
| 代理商： | CXD2728Q |
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– 32 –
CXD2728Q
(6) Passive Decoder (Surround Channel)
The surround channel is processed according to the flow shown in Fig. 8-1-3.
The setting method for each section is described below.
SP
–KS (f8H)
SO
7kHz
LPF
M-BNR
Delay
Fig. 8-1-3. Passive Decoder Signal Flow (S-ch)
0020H
0040H
·
·
52b0H
·
6e40H
·
89d0H
·
a560H
·
·
ff80H
ffa0H
Setting value Dly (fbH)
ON
OFF
df66
0000
b2
5723
0000
b1
125e
0000
a
eda2
8000
–a
0.022ms
0.045ms
·
·
15.000ms
·
20.000ms
·
25.000ms
·
30.000ms
·
·
46.349ms
46.372ms
Delay (fs = 44.1kHz)
Table 8-1-9. Surround Channel (S-ch) Delay Time Setting
Value Examples
(6)-1. Delay Time Setting
[Relevant data] Coefficient: Dly (fbH)
The surround channel delay time can be varied
by setting the coefficient Dly value. (Dly is the
delay line read address.)
Only the upper 11 of the 16 coefficient bits are
used. The lower 5 bits are not used, and are
ignored even if set.
That is to say, Dly can be set in 0020H
increments, and the delay time can be set in
approximately 0.022 ms increments.
The following condition also applies.
0020H
≤
Dly
≤
ffa0H
The coefficient value is calculated as follows.
(Dly)
Decimal
= (Delay [s])
×
fs [Hz]
×
32
Example)
For 20ms (fs = 44100 [Hz])
0.02
×
44100
×
32 = 28224 6e40H
(6)-2. 7kHz Low-Pass Filter
[Relevant data] Coefficients: b2 (afH), b1 (b0H), a (b1H), –a (b2H)
The 7kHz LPF of the passive decoder can be turned on and off by setting the coefficients in Table 8-1-10.
Table 8-1-10. Passive Decoder 7kHz LPF ON/OFF Setting
Hexadecimal conversion
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