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參數(shù)資料
| 型號(hào)： | CXD2724AQ-3 |
| 廠(chǎng)商： | Sony Corporation |
| 英文描述： | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞邏輯譯碼器) |
| 中文描述： | 單片杜比定向邏輯環(huán)繞聲解碼器（單片杜比環(huán)繞邏輯譯碼器） |
| 文件頁(yè)數(shù)： | 13/65頁(yè) |
| 文件大?。?/td> | 490K |
| 代理商： | CXD2724AQ-3 |
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CXD2724AQ-3
Description of Functions
1. Master/Slave Modes
[Relevant pins] XMST, LRCK, BCK
When using the CXD2724AQ -1 alone without digital input, set the CXD2724AQ-3 to master mode.
When using digital input, the CXD2724AQ-3 may be set to either master mode or slave mode.
The clock applied to LRCK and BCK in slave mode must be synchronized to either the crystal oscillator clock
of the XTLI and XTLO pins or the external clock input from the XTLI pin.
Table 1-1. LRCK, BCK Mode Setting
XMST
H
L
Mode
Slave mode
Master mode
LRCK, BCK I/O
Input
Output
SQC05
0
0
1
1
SQC04
0
1
0
1
BFOT
384fs
256fs
512fs
768fs
2. Master Clock System
[Relevant pins] XTLI, XTLO, BFOT
768fs (fs = 32 to 44.1kHz) is assumed for the master clock system, and the connection is as shown below.
BFOT outputs the clock obtained by frequency dividing the master clock. The frequency division ratio can be
changed by the setup register (SQC04, SQC05). (See "6. Setup Register".)
(1) Master
(2) Slave
O
I
O
Frequency
divider
Setup
Register
512fs
XTLI
XTLO
768fs
BFOT
256fs/384fs/512fs/768fs
O
512fs
XTLI
XTLO
768fs
I
OPEN
Frequency
divider
Fig. 2-1.
Note) Oscillation circuits may differ according to peripheral circuit and
substrate. Consult with crystal oscillator manufacturers about the
selecting oscillation circuits.
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| CXD2930BR | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:GPS LSI with Built-in 32-bit RISC CPU |
| CXD2931GA-9 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:RF/BASEBAND CIRCUIT|CMOS|LGA|144PIN|CERAMIC |
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