參數(shù)資料
型號(hào)： CXD2720Q-2
廠(chǎng)商： Sony Corporation
英文描述： CAP 10UF 50V 20% TANT SMD-7343-43 TR-13 GOLD
中文描述： 單片杜比定向邏輯環(huán)繞聲解碼器
文件頁(yè)數(shù)： 23/47頁(yè)
文件大?。?/td> 531K
代理商： CXD2720Q-2
– 23 –
CXD2720Q-2
(4)-2. Read
First, address section and mode section data are transmitted synchronized to SCK, and XLAT is raised
matched with this; the procedure until this point is the same as for write, so the description is omitted here.
Read differs from write in that after XLAT rise, REDY falls within 3
t
+ 50ns (
t
LBD
), and the microcomputer is
informed of SV cycle waiting.
At this time, the TRDT pin changes from high-impedance state to active state (
t
LDN
≤
3
t
+ 80ns) simultaneously
with REDY fall. When the read data is ready, the REDY pin changes from Low to High. When the data read out
from the TRDT pin is made TR, and SCK falls (
t
RSDP
≥
20ns) when the REDY pin goes High, the first TR data
is defined within 2
t
+ 70ns (
t
SDD
). The microcomputer reads this data at SCK rise. The TR data is read in order
from the LSB with 16 bits for the coefficient RAM and 24 bits for the setup register by adding SCK, the
corresponding data is all read, and then read is completed.
Next, the method for restarting transmission after read is completed is described.
As in Case 1, there is a method for sending address section and mode section data consecutively after reading
all of the 16- or 24-bit data. There should be 2
t
+ 40ns or more left between the SCK rise for the final data read
and the next SCK rise (
t
ss), and this is established by the conditions
t
SWL
≥
1
t
+ 20ns and
t
SWH
≥
1
t
+ 20ns.
Further, at this read REDY changes from High to Low, but it is prohibited for the XLAT for the next
transmission to fall before this. If REDY = Low has been verified, XLAT can fall (
t
LDR
≥
20 ns).
Also, while 16- or 24-bit data is being read from the TRDT pin, address and mode section data writing to the
RVDT pin for the next transmission can be started.
In Case 3, the final section of read data and the final data in the mode section overlap, and this allows shifting
to the next transmission processing in the shortest possible time after data read.
It is also possible to have data read and address and mode section write overlap partially, as shown in Case 2.
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