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參數(shù)資料
| 型號(hào)： | CXD2597Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁(yè)數(shù)： | 98/115頁(yè) |
| 文件大?。?/td> | 881K |
| 代理商： | CXD2597Q |
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– 98 –
CXD2597Q
$3C (preset: $3C 00 80)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COSS COTS
0
0
COT2 COT1 MOT2
0
BTS1 BTS0 MRC1 MRC0
0
0
0
0
COSS, COTS: These select the TZC signal used when generating the COUT signal.
Preset = HPTZC.
STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC is the delayed phase STZC. (The delay amount can be selected by D14 of $36.)
HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.
See §5-13.
These commands output the TZC signal.
COT2, COT1: This outputs the TZC signal from the COUT pin.
COSS
1
0
0
—
0
1
STZC
HPTZC
DTZC
COTS
TZC
: preset, —: don't care
BTS1
0
0
1
1
0
1
0
1
1
2
4
8
BTS0
Number of count-up steps per cycle
MRC1
0
0
1
1
0
1
0
1
5.669
11.338
22.675
45.351
MRC0
Setting time [μs]
: preset (when MCK = 128Fs)
MOT2:
The STZC signal is output from the MIRR pin by setting MOT2 to 1.
These commands set the MIRR signal generation circuit.
BTS1, BTS0:
This sets the count-up speed for the bottom hold value of the MIRR generation circuit.
The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1,
BTS0 = 0. However, this is valid only when BTF of $3B is 0.
MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.
As noted in §5-9, the MIRR signal is generated by comparing the waveform obtained by
subtracting the bottom hold value from the peak hold value with the MIRR comparator level.
Strictly speaking, however, for MIRR to become high, these levels must be compared
continuously for a certain time. This sets that time.
The preset value is MRC1 = 0, MRC0 = 0.
COT2
1
0
0
—
1
0
STZC
HPTZC
COUT
COT1
COUT pin output
: preset, —: don't care
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