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參數(shù)資料
| 型號(hào)： | CXD2597Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁(yè)數(shù)： | 80/115頁(yè) |
| 文件大?。?/td> | 881K |
| 代理商： | CXD2597Q |
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CXD2597Q
AGCNTL and default operation have two stages.
In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select
256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.
The sensitivity at this time can be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with
relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the
second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops
changing, the CXD2597Q confirms that the AGCNTL coefficient has not changed for a certain period of time
(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 5-5.
Initial value
SENS
AGCNTL
Start
AGCNTL
completion
Convergence value
AGCNTL
coefficient value
Slope AGV1
AGHT
AGJ
Slope AGV2
Fig. 5-5.
Note)
Fig. 5-5 shows the example where the AGCNTL coefficient value converges to the smaller value from
the initial value.
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