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參數(shù)資料
| 型號(hào)： | CXD2597Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁數(shù)： | 87/115頁 |
| 文件大?。?/td> | 881K |
| 代理商： | CXD2597Q |
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CXD2597Q
§5-15. Writing to Coefficient RAM
The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40μs (when MCK = 128Fs) after the XRST pin
rises. (The coefficient RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as data. Coefficient rewriting is completed 11.3μs (when MCK = 128Fs) after the command is
received. When rewriting multiple coefficients continuously, be sure to wait 11.3μs (when MCK = 128Fs)
before sending the next rewrite command.
§5-16. PWM Output
FCS, TRK and SLD outputs are output as PWM waveforms.
In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper.
Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits.
t
MCK
= 1
≈
180ns
5.6448MHz
Timing Chart 5-20.
64t
MCK
64t
MCK
64t
MCK
At
MCK
At
MCK
SFDR
SRDR
SLD
32t
MCK
32t
MCK
32t
MCK
32t
MCK
32t
MCK
32t
MCK
FCS/TRK
FFDR/
TFDR
FRDR/
TRDR
Output value +A
Output value –A
Output value 0
t
MCK
A
2
t
MCK
A
2
t
MCK
A
2
t
MCK
A
2
MCK
(5.6448MHz)
↑
↑
↑
↑
↑
↑
↑
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