參數(shù)資料
型號(hào)： CXD2587Q
廠商： Sony Corporation
元件分類： 數(shù)字信號(hào)處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述： CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù)： 68/106頁
文件大小： 807K
代理商： CXD2587Q
– 68 –
CXD2587Q
§4-4. E:F Balance Adjustment Function
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value
(subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 4-3.)
§4-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 4-3.)
When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit
value of D9 to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing
Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions
as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops if the FBIAS value and the value set beforehand
in FBL9 to 1 of $34 match. Also, if the upper 8 bits of the command register are $3A at this time, SENS
becomes high and the counter stop can be monitored.
A
B
C
FBIAS setting value (FB9 to 1)
LIMIT value (FBL9 to 1)
SENS pin
A: Register mode
B: Counter mode
C: Counter mode (when stopped)
Here, assume the FBIAS setting value FB9 to 1
and the FBIAS LIMIT value FBL9 to 1 like status
A. For example, if command registers FBUP = 0,
FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from
this status, down count starts from status A and
approaches the set LIMIT value. When the
FBIAS value matches FBL9 to 1, the counter
stops and the SENS pin goes to high. Note that
the up/down counter counts at each sampling
cycle of the focus servo filter. The number of
steps by which the count value changes can be
selected from 1, 2, 4 or 8 steps by FBV1 and
FBV0. When converted to FE input, 1 step
corresponds to 1/512
×
V
DD
×
0.4.
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